go
英文: Inside an always@(posedge clk) block, having a nested for loop, how do we output for each and ev...
59image-processing
output
go
英文: Need help in converting verilog module without input & output ports into synthesizable. Beca...
55image
system-verilog
go
英文: How to Read Data from a specific address of the FPGA QSPI Flash board? 问题 I'm new to Vitis and X...
51fpga
spi
go
英文: Vitis HLS 2022.2 ERROR: [HLS 200-1715] Encountered problem during source synthesis 问题 我是一名Vitis ...
58vivado-hls
xilinx
go
英文: Linux Kernel Boot Error: reserving fdt memory region failed 问题 The boot error you mentioned, &qu...
194linux-kernel
memory
go
英文: How to get access to Xilinx FPGA temperature in hdl code? 问题 我正在使用赛灵思超标 FPGA（具体来说，AXKU-040）。我参与的...
48fpga
xilinx
go
英文: Interrupt in Microblaze on AXI_GPIO (XILINX FPGA) 问题 I study to work with FPGA (Xilinx Kintex Ul...
52interrupt
vhdl
go
英文: Division in Verilog and Q factor representation 问题 I am currently working on a design of an algo...
97signal-processing
verilog
59评论image-processing
output