在一个始终@(posedge clk)块内,有一个嵌套的for循环,如何输出每个i和j的值?

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英文:

Inside an always@(posedge clk) block, having a nested for loop, how do we output for each and every values of i and j?

问题

To achieve the desired output, you can add a condition to check for specific values of i and j before displaying the result. Here's the modified code:

integer i, j;
reg [15:0] Y_Planar_Prediction_reg; // Register to store Y_Planar_Prediction

always @(posedge clk) begin
    for (j = 0; j < 16; j = j + 1) begin
        for (i = 0; i < 16; i = i + 1) begin
            Y_pred_h = (16 - 1 - i) * Y_ref_buffer_left[j] + (i + 1) * Y_ref_buffer_top_right;
            Y_pred_v = (16 - 1 - j) * Y_ref_buffer_top[i] + (j + 1) * Y_ref_buffer_left_bottom;
            Y_Planar_Prediction = (Y_pred_h + Y_pred_v + 16) >> (4 + 1);

            // Check for specific i and j values
            if (i == 0 && j == 0) begin
                Y_Planar_Prediction_reg <= Y_Planar_Prediction;
                $display("@%dns Y_Planar_Prediction for i=0, j=0: %d", $time, Y_Planar_Prediction_reg);
            end
            else if (i == 1 && j == 0) begin
                Y_Planar_Prediction_reg <= Y_Planar_Prediction;
                $display("@%dns Y_Planar_Prediction for i=1, j=0: %d", $time, Y_Planar_Prediction_reg);
            end
            else if (i == 2 && j == 0) begin
                Y_Planar_Prediction_reg <= Y_Planar_Prediction;
                $display("@%dns Y_Planar_Prediction for i=2, j=0: %d", $time, Y_Planar_Prediction_reg);
            end
            // Add more conditions for other values of i and j as needed
        end
    end
end

This modified code checks for specific values of i and j and displays the Y_Planar_Prediction result with the corresponding time and values of i and j. You can extend this pattern for other values of i and j as required.

英文:

Code

integer i,j;

//Luma
always @(posedge clk)
begin
	for (j=0; j&lt;16; j=j+1)	
	begin
		for (i=0; i&lt;16; i=i+1) 
		begin
			Y_pred_h = (16-1-i) * Y_ref_buffer_left[j] + (i+1) * Y_ref_buffer_top_right;
			Y_pred_v = (16-1-j) * Y_ref_buffer_top[i] + (j+1) * Y_ref_buffer_left_bottom;
			Y_Planar_Prediction = (Y_pred_h + Y_pred_v + 16 ) &gt;&gt; (4+1);				
		end
	end
end

Here Y_Planar_Prediction is my module output, and I need to display its result on screen for each and every value of i and j in every posedge of clk (i.e for i=0,j=0 at time=15; i=1,j=0 at time=25; i=2,j=0 at time=35;.....; i=5,j=10 at time=something; ..........; i=15,j=15 at time=something)

But, when I simulate observing the output for only i=15,j=15 (i.e 158) in every posedge of clk.

Attached screenshot for reference:

在一个始终@(posedge clk)块内,有一个嵌套的for循环,如何输出每个i和j的值?

How can i modify the code to get:

@15ns Y_Planar_Prediction for i=0,j=0; 
@25ns Y_Planar_Prediction for i=1,j=0; 
@35ns Y_Planar_Prediction for i=2,j=0;
and so on...

答案1

得分: 1

Verilog中的for循环只是一种编写简洁代码的便捷方式。ij变量只是循环索引,其值在一个模拟时间步骤内更改。模拟的行为符合预期。这不是for循环的正确用法。

看起来你确实希望ij推断计数器的逻辑,而不是使用for循环。在这种情况下,你需要添加新的always块。例如:

reg [3:0] icnt;
always @(posedge clk) begin
    if (icnt_en) icnt <= icnt + 1;
end

这样,icnt将在每个时钟周期上具有新的值。

英文:

for loops in Verilog are merely a convenient way to write concise code. The i and j variables are just loop indexes whose values change in a single simulation time step. The simulation is behaving as expected. This is not a proper use of for loops.

It seems like you really want i and j to infer logic of counters instead of using for loops. In that case you would need to add new always blocks. For example:

reg [3:0] icnt;
always @(posedge clk) begin
    if (icnt_en) icnt &lt;= icnt + 1;
end

In this way, icnt will have a new value on each clock cycle.

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  • 本文由 发表于 2023年6月1日 00:21:20
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