英文:
Interrupt in Microblaze on AXI_GPIO (XILINX FPGA)
问题
I study to work with FPGA (Xilinx Kintex Ultrascale).
In Vivado, I create a block design with my module (gen_data) and Microblaze (soft processor for XILINX FPGA).
Connect with Microblaze across AXI_GPIO (have 1 input and Interrupt Enable).
Gen_data is a simple module (source code).
Frequency is 100 Mhz.
entity generate_data is
port (
clk : in std_logic;
out_data : out std_logic
);
end generate_data;
architecture Behavioral of generate_data is
begin
process (clk)
variable counter : integer := 0;
begin
if rising_edge(clk) then
counter := counter + 1;
if counter = 100000 then
out_data <= '1';
counter := 0;
end if;
end if;
end process;
end Behavioral;
On the Microblaze side, I set up an interrupt, but it doesn't work.
What do I need to do to make the interrupt work with the gen_data module? Thanks.
But if I change my module (gen_data) to some button, then the interrupt will work well. For AXI_GPIO, the button is a 1-input bit (similar to gen_data).
英文:
I study to work with FPGA (Xilinx Kintex Ultrascale).
In Vivado i create blockdesign with my module (gen_data) and Microblaze (soft processor for XILINX fpga).
Connect with Microblaze across AXI_GPIO (have 1 input and Interrupt Enable).
Gen_data is simple module (source code).
Frequency is 100 Mhz.
entity generate_data is
port (
clk : in std_logic;
out_data : out std_logic
);
end generate_data;
architecture Behavioral of generate_data is
begin
process (clk)
variable counter : integer := 0;
begin
if rising_edge(clk) then
counter := counter + 1;
if counter = 100000 then
out_data <= '1';
counter := 0;
end if;
end if;
end process;
end Behavioral;
On Microblaze side i set interrupt but it is doesnt work.
What i need to do for work interrupt with module gen_data? Thanks.
But if i change my module (gen data) on some button then interrupt will work good.
For AXI_GPIO button is 1 input bit (similar to gen_data).
答案1
得分: 1
你从未将 data_out 设置为 '0'，所以一旦它变为1，它将永远保持在那里。 以下代码将 data_out 设置为 '0'，并将 "count := count + 1" 移动，以便检查 counter = 100000 是针对寄存器输出而不是新递增的值。
entity generate_data is
port (
clk : in std_logic;
out_data : out std_logic
);
end generate_data;
architecture Behavioral of generate_data is
begin
process (clk)
variable counter : integer := 0;
begin
if rising_edge(clk) then
if counter = 100000 then
out_data <= '1';
counter := 0;
else
out_data <= '0';
counter := counter + 1;
end if;
end if;
end process;
end Behavioral;
英文:
You never set data_out to '0' so once it goes to 1, it stays there forever. The following drives data_out to '0' and moves "count := count + 1" so that the check, counter = 100000, is against the register output rather than the newly incremented value.
entity generate_data is
port (
clk : in std_logic;
out_data : out std_logic
);
end generate_data;
architecture Behavioral of generate_data is
begin
process (clk)
variable counter : integer := 0;
begin
if rising_edge(clk) then
if counter = 100000 then
out_data <= '1';
counter := 0;
else
out_data <= '0';
counter := counter + 1
end if;
end if;
end process;
end Behavioral;
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