go
英文: If I use a blocking expression in the covergroup, do I need a sample directive from the previous...
173system-verilog
uvm
go
英文: Why does my FSM not result in combinational logic? 问题 I'm trying to make a fsm and decoder file....
122system-verilog
vivado
go
英文: Use of disable fork inside forever loop of fork-join 问题 在上述任务中，一旦ack_arrival完成，"disable for...
118system-verilog
go
英文: How to access signals in submodules with multiple modules? 问题 I have the following Verilog file ...
131system-verilog
verilog
go
英文: Getting Z values when expecting a proper output 问题 以下是您的代码的翻译部分： module ECE228_2( input [7:0] A,...
114system-verilog
verilog
go
英文: SV randomization - generating non-overlapping memory regions using constraints 问题 以下是您要翻译的部分： 这个...
107constraints
system-verilog
go
英文: How to correctly calculate the frequency of the device in Timing Analyzer, Intel Quartus 问题 I ha...
113system-verilog
verilog
go
英文: Real value printed with %f is 0.0000, but condition '>0' does not apply (after using ...
116system-verilog
verilog
go
英文: EDA playground ERROR VCP5294 "Undefined package uvm_pkg" 问题 我正在尝试在EDA playground中编译一个小...
117system-verilog
uvm
go
英文: How to create an array of interface of different size in system verilog 问题 我有一个可配置的模块，其中包含一个端口的接...
180system-verilog
verilog
173评论system-verilog
uvm