英文:
EDA playground ERROR VCP5294 "Undefined package uvm_pkg"
问题
我正在尝试在EDA playground中编译一个小的UVM验证环境。
我遇到了这个错误：
EDA playground ERROR VCP5294 "Undefined package uvm_pkg.
以下是附加的代码：
import uvm_pkg::*;
`include "reg_pkg.sv"
module testbench;
reg rst;
reg clk;
always #50 clk = ~clk;
initial begin
rst=0;
clk=0;
#100;
rst = 1;
`uvm_info("TESTBENCH",$sformatf("rst raised"),UVM_NONE);
end
reg_if reg_if_i();
assign reg_if_i.clk = clk;
assign reg_if_i.rst = rst;
WriteRegisters WriteRegisters_i(
.clk(reg_if_i.clk),
.rst(reg_if_i.rst),
.bus_en(reg_if_i.bus_en),
.bus_wr_rd(reg_if_i.bus_wr_rd),
.bus_data(reg_if_i.bus_data),
.bus_addr(reg_if_i.bus_addr)
);
initial begin
uvm_config_db#(virtual mux_if)::set(null,"*","reg_if_i",reg_if_i);
$dumpvars(0, testbench);
end
initial begin
run_test("reg_test1");
end
endmodule
你知道我为什么会得到这个错误吗？
英文:
I'm trying to compile a small UVM verification environment in EDA playground.
I'm getting this error:
> EDA playground ERROR VCP5294 "Undefined package uvm_pkg.
The code attached below:
import uvm_pkg::*;
`include "reg_pkg.sv"
module testbench;
reg rst;
reg clk;
always #50 clk = ~clk;
initial begin
rst=0;
clk=0;
#100;
rst = 1;
`uvm_info("TESTBENCH",$sformatf("rst raised"),UVM_NONE);
end
reg_if reg_if_i();
assign reg_if_i.clk = clk;
assign reg_if_i.rst = rst;
WriteRegisters WriteRegisters_i(
.clk(reg_if_i.clk),
.rst(reg_if_i.rst),
.bus_en(reg_if_i.bus_en),
.bus_wr_rd(reg_if_i.bus_wr_rd),
.bus_data(reg_if_i.bus_data),
.bus_addr(reg_if_i.bus_addr)
);
initial begin
uvm_config_db#(virtual mux_if)::set(null,"*","reg_if_i",reg_if_i);
$dumpvars(0, testbench);
end
initial begin
run_test("reg_test1");
end
endmodule
Do you know why I get this error?
答案1
得分: 1
在使用EDA Playground上的UVM时，您需要在左侧面板中明确选择一个UMV库版本。当前的"UVM/OVM"设置为None。
当我将其设置为UVM 1.2时，错误消失了，如下所示：
[2023-01-08 09:29:19 EST] vlib work && vlog '-timescale' '1ns/1ns' +incdir+$RIVIERA_HOME/vlib/uvm-1.2/src -l uvm_1_2 -err VCP2947 W9 -err VCP2974 W9 -err VCP3003 W9 -err VCP5417 W9 -err VCP6120 W9 -err VCP7862 W9 -err VCP2129 W9 design.sv testbench.sv && vsim -c -do "vsim +access+r; run -all; exit"
VSIMSA: 配置文件已更改：`/home/runner/library.cfg'
ALIB: 已连接库"work"。
work = /home/runner/work/work.lib
MESSAGE "Pass 1. Scanning modules hierarchy."
MESSAGE_SP VCP2124 "在库uvm_1_2中找到包uvm_pkg。"
这是修改后的EDA Playground链接。
在左侧面板的示例中也有帮助：Examples -> UVM -> UVM Hello World
英文:
When using UVM on EDA Playground, you need to explicitly select a UMV library version in the left side panel. Currently "UVM/OVM" is set to None.
When I set it to UVM 1.2, the error goes away, as you can see below:
[2023-01-08 09:29:19 EST] vlib work && vlog '-timescale' '1ns/1ns' +incdir+$RIVIERA_HOME/vlib/uvm-1.2/src -l uvm_1_2 -err VCP2947 W9 -err VCP2974 W9 -err VCP3003 W9 -err VCP5417 W9 -err VCP6120 W9 -err VCP7862 W9 -err VCP2129 W9 design.sv testbench.sv && vsim -c -do "vsim +access+r; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library "work" attached.
work = /home/runner/work/work.lib
MESSAGE "Pass 1. Scanning modules hierarchy."
MESSAGE_SP VCP2124 "Package uvm_pkg found in library uvm_1_2."
Here is the modified EDA Playgound link.
It is also helpful to look at the examples in the left side panel: Examples -> UVM -> UVM Hello World
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