英文:
How to create an array of interface of different size in system verilog
问题
我有一个可配置的模块,其中包含一个端口的接口。我使用generate语句和for循环来创建每个模块实例的不同配置,并将接口端口导出到一个数组中。我的问题是,根据每个模块实例的配置,各个接口是不同的。是否有一种方法可以单独配置数组中的每个接口?这是我正确配置接口的方式:
test_if #(.NUM_CUTS(NUM_CUTS_WRITE_CLIENT), .AW(AW_WRITE_CLIENT), .DW(DW_WRITE_CLIENT)) mem_test_if [NUM_OF_MEMS-1:0]();
是否可能像这样使用接口数组进行某种配置:
test_if #(.NUM_CUTS(2), .AW(AW_WRITE_CLIENT), .DW(DW_WRITE_CLIENT)) mem_test_if [0]();
test_if #(.NUM_CUTS(4), .AW(AW_WRITE_CLIENT), .DW(DW_WRITE_CLIENT)) mem_test_if [1]();
test_if #(.NUM_CUTS(6), .AW(AW_WRITE_CLIENT), .DW(DW_WRITE_CLIENT)) mem_test_if [2]();
我不想在generate语句之外单独实例化每个模块实例。
英文:
I have a configurable module which contains an interface for one of the ports. I use a generate statement and a for loop to create different configuration of each module instance and I bring the interface ports out in an array. My issue is the individual interfaces are different based of the config of each module instance. Is there a way to configure each interface in the array individually? This is how I correctly configure the interface
test_if #(.NUM_CUTS(NUM_CUTS_WRITE_CLIENT),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if [NUM_OF_MEMS-1:0]();
Is it possible to do something like this with an array of interfaces
test_if #(.NUM_CUTS(2),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if [0]();
test_if #(.NUM_CUTS(4),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if [1]();
test_if #(.NUM_CUTS(6),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if [2]();
I don't want to have to instantiate each module instance separately outside of the generate statement.
答案1
得分: 2
你应该能够在你的generate块中嵌套完成这个操作:
for(genvar MEM=0;MEM<NO_OF_MEMS;MEM++) begin : ID
test_if #(.NUM_CUTS((MEM+1)*2),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if();
end
英文:
You should be able to do this nested inside your generate
for(genvar MEM=0;MEM<NO_OF_MEMS;MEM++) begin : ID
test_if #(.NUM_CUTS((MEM+1)*2),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if();
end
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