问题

有多个模块，其中我以输入的形式（除其他事项外）获取以下内容：

``` lang-sv
input[15:0] instruction

然后，在所有这些模块中，我都复制并粘贴以下代码：

wire aluBit = instruction[15];
wire jumpBit = instruction[14];
wire[2:0] mainOpcode = instruction[13:11];
wire constantBit = instruction[10];
wire standaloneBit = instruction[9];
wire[7:0] embeddedConstant = instruction[9:3];
wire[2:0] instrParam1 = instruction[8:6];
wire[2:0] instrParam2 = instruction[5:3];
wire[2:0] instrDestination = instruction[2:0];

我认为接口可以使这个过程更加流畅，并消除复制粘贴。但我不明白如何使其工作。

注意：如果有帮助的话，我正在使用一个名为sv2v的SystemVerilog到Verilog转换器。

我尝试了很多次，例如：

interface Instruction;
    logic[15:0] instruction;
    logic aluBit, jumpBit, isConstantInstruction, standaloneBit;
    logic[2:0] mainOpcode, instrParam1, instrParam2, instrDestination;
    logic[7:0] embeddedConstant;

    always_comb aluBit = instruction[15];
    always_comb jumpBit = instruction[14];
    always_comb mainOpcode = instruction[13:11];
    always_comb isConstantInstruction = instruction[10];
    always_comb standaloneBit = instruction[9];
    always_comb embeddedConstant = instruction[9:3];
    always_comb instrParam1 = instruction[8:6];
    always_comb instrParam2 = instruction[5:3];
    always_comb instrDestination = instruction[2:0];
endinterface

然后，我尝试定义ControlUnit模块，带有Instruction输入端口：

module ControlUnit(Instruction instruction);
    wire example = instruction.jumpBit;
    ...
endmodule

但它却无法编译。

<details>
<summary>英文:</summary>

There are multiple modules where I take as input (among other things) a

``` lang-sv
input[15:0] instruction

Then, in all these modules I copy and paste the following code:

wire aluBit = instruction[15];
wire jumpBit = instruction[14];
wire[2:0] mainOpcode = instruction[13:11];
wire constantBit = instruction[10];
wire standaloneBit = instruction[9];
wire[7:0] embeddedConstant = instruction[9:3];
wire[2:0] instrParam1 = instruction[8:6];
wire[2:0] instrParam2 = instruction[5:3];
wire[2:0] instrDestination = instruction[2:0];

I believe interfaces would streamline this and get rid of the copy-pasting. But I don't understand how to make it work.

Note: If it helps, I am using a SystemVerilog to Verilog converter called sv2v.

I tried alot, for example:

interface Instruction;
    logic[15:0] instruction,
    logic aluBit, jumpBit, isConstantInstruction, standaloneBit,
    logic[2:0] mainOpcode, instrParam1, instrParam2, instrDestination,
    logic[7:0] embeddedConstant

    always_comb aluBit = instruction[15];
    always_comb jumpBit = instruction[14];
    always_comb mainOpcode = instruction[13:11];
    always_comb isConstantInstruction = instruction[10];
    always_comb standaloneBit = instruction[9];
    always_comb embeddedConstant = instruction[9:3];
    always_comb instrParam1 = instruction[8:6];
    always_comb instrParam2 = instruction[5:3];
    always_comb instrDestination = instruction[2:0];
endinterface

Then I tried to define the ControlUnit module, with an Instruction input port:

module ControlUnit(Instruction instruction);
    wire example = instruction.jumpBit;
    ...
endmodule

It just does not compile though.

答案1

得分: 0

以下是翻译好的部分：

这是一个interface定义的示例（使用OP作为基线），以及将其用作module port的用法，将interface视为一组没有端口的电线捆绑（这意味着接口本身没有端口）。

发布的代码在开始附近的电线上缺少分号。

• 在接口上添加了分号
• 声明了interface（必须在module之外定义，module和interface都是基本的设计单元）
• 创建了带有interface端口的module ControlUnit，并打印了一些interface值。
• 在测试台中实例化了somemodule
• 声明了一个接口类型的变量以连接到模块端口
• 使用常数驱动接口变量
• 将接口变量连接到测试台DUT
• 运行了测试台

接口：

interface Instruction ();
    logic[15:0] instruction;
    logic aluBit, jumpBit, isConstantInstruction, standaloneBit;
    logic[2:0] mainOpcode, instrParam1, instrParam2, instrDestination;
    logic[7:0] embeddedConstant;

    always_comb aluBit = instruction[15];
    always_comb jumpBit = instruction[14];
    always_comb mainOpcode = instruction[13:11];
    always_comb isConstantInstruction = instruction[10];
    always_comb standaloneBit = instruction[9];
    always_comb embeddedConstant = instruction[9:3];
    always_comb instrParam1 = instruction[8:6];
    always_comb instrParam2 = instruction[5:3];
    always_comb instrDestination = instruction[2:0];
endinterface

模块：

module ControlUnit(
  Instruction instruction
  );
  
    wire example = instruction.jumpBit;
  
  initial begin
    #1;
    $display("instruction.jumpBit = %0b",instruction.jumpBit);
    $display("instruction.aluBit = %0b",instruction.aluBit);
  end
  
endmodule

测试台：

module tb ();
  
  Instruction tb_stub();
  
  assign tb_stub.instruction = 16'h5a5a;
  
  ControlUnit dut(
   .instruction(tb_stub)
  );

endmodule

在Cadence、Mentor、Synopsys和Aldec模拟器上运行时，会产生以下输出：

instruction.jumpBit = 0
instruction.aluBit = 1

interface Instruction ();
    logic[15:0] instruction;
    logic aluBit, jumpBit, isConstantInstruction, standaloneBit;
    logic[2:0] mainOpcode, instrParam1, instrParam2, instrDestination;
    logic[7:0] embeddedConstant;

    always_comb aluBit = instruction[15];
    always_comb jumpBit = instruction[14];
    always_comb mainOpcode = instruction[13:11];
    always_comb isConstantInstruction = instruction[10];
    always_comb standaloneBit = instruction[9];
    always_comb embeddedConstant = instruction[9:3];
    always_comb instrParam1 = instruction[8:6];
    always_comb instrParam2 = instruction[5:3];
    always_comb instrDestination = instruction[2:0];
endinterface

module ControlUnit(
  Instruction instruction
  );
  
    wire example = instruction.jumpBit;
  
  initial begin
    #1;
    $display("instruction.jumpBit = %0b",instruction.jumpBit);
    $display("instruction.aluBit = %0b",instruction.aluBit);
  end
  
endmodule 

module tb ();
  
  Instruction tb_stub();
  
  assign tb_stub.instruction = 16'ha5a5;
  
  ControlUnit dut(
   .instruction(tb_stub)
  );

endmodule   

instruction.jumpBit = 0
instruction.aluBit = 1