英文:
Error: object on left-hand side of assignment must have a net type
问题
以下是您提供的 Verilog 代码的翻译部分:
我刚开始使用Verilog,我得到了一些实现UART的代码。我认为可能缺少某些东西,因为我收到了下面显示的编译错误:
错误(10219):在Uart8Transmitter.v(26)处的Verilog HDL连续赋值错误:赋值左侧的对象“idx”必须具有网络类型
以下是代码:
模块Uart8Transmitter (
输入 导线 clk, //波特率
输入 导线 en,
输入 导线 start, //事务开始
输入 导线 [7:0] in, //要传输的数据
输出 寄存器 out, // tx
输出 寄存器 done, //交易结束
输出 寄存器 busy //交易正在进行中
);
寄存器 [2:0] 状态 = `RESET;
寄存器 [7:0] 数据 = 8'b0; //存储输入数据的副本
寄存器 [2:0] bitIdx = 3'b0; //用于8位数据
寄存器 [2:0] idx;
分配 idx = bitIdx;
始终 @(posedge clk) 开始
case (状态)
默认 : 开始
状态 <= `IDLE;
结束
`IDLE : 开始
out <= 1'b1; //将线路拉高以保持空闲状态
done <= 1'b0;
busy <= 1'b0;
bitIdx <= 3'b0;
数据 <= 8'b0;
如果 (start & en) 开始
数据 <= in; //保存输入数据的副本
状态 <= `START_BIT;
结束
结束
`START_BIT : 开始
out <= 1'b0; //发送起始位(低位)
busy <= 1'b1;
状态 <= `DATA_BITS;
结束
`DATA_BITS : 开始 //等待8个时钟周期以发送数据位
out <= 数据[idx];
如果 (&bitIdx) 开始
bitIdx <= 3'b0;
状态 <= `STOP_BIT;
否则 开始
bitIdx <= bitIdx + 1'b1;
结束
结束
`STOP_BIT : 开始 //发送停止位(高位)
done <= 1'b1;
数据 <= 8'b0;
状态 <= `IDLE;
结束
endcase
结束
结束模块
希望这有助于您解决问题。如果您有其他问题,请随时提出。
英文:
I am new to working with Verilog, and I was given some code that implements uart. I think it might be missing something since I am getting the compiling error shown below:
Error (10219): Verilog HDL Continuous Assignment error at Uart8Transmitter.v(26): object "idx" on left-hand side of assignment must have a net type
The code is shown below:
module Uart8Transmitter (
input wire clk, // baud rate
input wire en,
input wire start, // start of transaction
input wire [7:0] in, // data to transmit
output reg out, // tx
output reg done, // end on transaction
output reg busy // transaction is in process
);
reg [2:0] state = `RESET;
reg [7:0] data = 8'b0; // to store a copy of input data
reg [2:0] bitIdx = 3'b0; // for 8-bit data
//reg [2:0] idx;
//wire idx; //added
reg [2:0] idx;
assign idx = bitIdx;
always @(posedge clk) begin
case (state)
default : begin
state <= `IDLE;
end
`IDLE : begin
out <= 1'b1; // drive line high for idle
done <= 1'b0;
busy <= 1'b0;
bitIdx <= 3'b0;
data <= 8'b0;
if (start & en) begin
data <= in; // save a copy of input data
state <= `START_BIT;
end
end
`START_BIT : begin
out <= 1'b0; // send start bit (low)
busy <= 1'b1;
state <= `DATA_BITS;
end
`DATA_BITS : begin // Wait 8 clock cycles for data bits to be sent
out <= data[idx];
if (&bitIdx) begin
bitIdx <= 3'b0;
state <= `STOP_BIT;
end else begin
bitIdx <= bitIdx + 1'b1;
end
end
`STOP_BIT : begin // Send out Stop bit (high)
done <= 1'b1;
data <= 8'b0;
state <= `IDLE;
end
endcase
end
endmodule
Can anyone help me resolve this?
答案1
得分: 2
Verilog assign
将值分配给线而不是寄存器/变量。 代码在其他地方使用 idx 作为变量,因此需要将其作为变量而不是线来建模逻辑:
// assign idx = bitIdx;
always @*
idx = bitIdx;
英文:
Verilog assign
assigns to wires not to reg's/variables.
The code uses idx as a variable in other places, therefore it's needed as a variable rather than a wire.
Model the logic this way:
//assign idx = bitIdx;
always @*
idx = bitIdx;
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