Ring FIFO 模拟中的未定义输出

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英文:

Undefined output in Ring FIFO simulation

问题

这是您提供的SystemVerilog代码的翻译部分：

  1. 我一直在为SystemVerilog编写FIFO。最初的模拟结果还不错。然而，当我扩展模拟以尝试将其推向极限并考虑边界情况时，我遇到了一些问题。尽管我已经能够解决其中大多数，但有一个问题我一直没有解决。
  3. //此FIFO实现了循环缓冲拓扑结构
  4. //注意：FIFO的定义方式使得深度为1是不可能的
  5. //这是因为指针将始终位于相同的位置
  6. //因此FIFO始终是"空的"
  7. module i2s_fifo #(
  8.     parameter WIDTH = 16,
  9.     parameter DEPTH = 10
  10. )(
  11.     input logic clk_i,
  12.     input logic rst_ni,
  14.     //写通信信号
  15.     output logic wready,
  16.     input logic wvalid,
  17.     input logic [WIDTH-1:0] fifo_data_in,
  19.     //读通信信号
  20.     input logic rready,
  21.     output logic rvalid,
  22.     output logic [WIDTH-1:0] fifo_data_out,
  24.     //调试
  25.     output logic [$clog2(DEPTH)-1:0] wptr_tb,
  26.     output logic [$clog2(DEPTH)-1:0] rptr_tb
  27. );
  28.     //这返回需要添加X大小的地址所需的位数
  29.     //例如，$clog2(7) = 3。我们需要三位来访问7个值的存储器。
  30.     //基本上是从整数转换为位数
  31.     localparam int unsigned byte_depth = $clog2(DEPTH);
  33.     //指针
  34.     logic [byte_depth-1:0] fifo_rptr, fifo_wptr; 
  35.     assign wptr_tb = fifo_wptr;
  36.     assign rptr_tb = fifo_rptr;
  37.     
  39.     //如果FIFO为空，我们不能读取
  40.     //如果FIFO已满，我们不能写入
  41.     logic fifo_empty;
  42.     logic fifo_full;
  44.     always_comb begin : fifo_state   
  45.         if(fifo_rptr == fifo_wptr) begin
  46.             assign fifo_empty = 1'b1;
  47.         end else begin
  48.             assign fifo_empty = 1'b0;
  49.         end
  51.         if(fifo_wptr == DEPTH)begin //指针位于FIFO的边缘
  52.             if (fifo_rptr == 0) begin 
  53.                 fifo_full <= 1'b1;
  54.             end else begin
  55.                 fifo_full <= 1'b0;
  56.             end
  57.         end else if (fifo_wptr+1 == fifo_rptr)begin
  58.             fifo_full <= 1'b1;
  59.         end else begin
  60.             fifo_full <= 1'b0;
  61.         end
  62.     end
  64.     //握手
  65.     logic revent, wevent;
  67.     assign rvalid = !fifo_empty;
  68.     assign revent = rvalid && rready;
  70.     assign wready = !fifo_full;
  71.     assign wevent = wvalid && wready;
  73.     //增加指针位置
  74.     always_ff @(posedge clk_i) begin
  75.         if(!rst_ni)begin
  76.             fifo_rptr <= {(byte_depth){1'b0}};
  77.         end else if (revent) begin
  78.             if (fifo_rptr == DEPTH) begin
  79.                 fifo_rptr <= {(byte_depth){1'b0}};
  80.             end else begin
  81.                 fifo_rptr <= fifo_rptr+1;
  82.             end
  83.         end
  84.     end
  86.     always_ff @(posedge clk_i) begin
  87.         if(!rst_ni)begin
  88.             fifo_wptr <= {(byte_depth){1'b0}};
  89.         end else if (wevent) begin
  90.             if (fifo_wptr == DEPTH) begin
  91.                 fifo_wptr <= {(byte_depth){1'b0}};
  92.             end else begin
  93.                 fifo_wptr <= fifo_wptr+1;
  94.             end
  95.         end
  96.     end
  98.     //写入和保存数据
  99.     //数据类型  [行][列] 数组名称;
  100.     logic [DEPTH-1:0] [(WIDTH-1):0] fifo_storage;
  102.     always_ff @(posedge clk_i)begin
  103.         if(wevent) begin
  104.             //这访问由指针指定的行
  105.             fifo_storage[fifo_wptr] <= fifo_data_in;
  106.         end
  107.     end
  109.     always_ff @(posedge clk_i)begin
  110.         if(revent) begin
  111.             fifo_data_out <= fifo_storage[fifo_rptr];
  112.         end
  113.     end    
  114. endmodule

这是测试台部分的翻译：

  1. module i2s_fifo_tb(
  3. );
  4.     localparam WIDTH = 16;
  5.     localparam DEPTH = 10;
  6.     logic clk;
  7.     logic rst;
  8.     logic wready;
  9.     logic wvalid;
  10.     logic [WIDTH-1:0] fifo_data_in;
  11.     logic rready;
  12.     logic rvalid;
  13.     logic [WIDTH-1:0] fifo_data_out;
  14.     logic [$clog2(DEPTH)-1:0] rptr_tb;
  15.     logic [$clog2(DEPTH)-1:0] wptr_tb;
  16.     i2s_fifo #(
  17.         .WIDTH(16),
  18.         .DEPTH(10)
  19.     )UUT(
  20.         .clk_i(clk),
  21.         .rst_ni(rst),
  22.         .wready,
  23.         .wvalid,
  24.         .fifo_data_in,
  25.         .fifo_data_out,
  26.         .rready,
  27.         .rvalid,
  28.         .rptr_tb,
  29.         .wptr_tb
  30.     );
  31.     always begin
  32.         clk = '1;
  33.         #10000;
  34.         clk = '0;
  35.         #10000;
  36.     end
  37.     
  38.     initial begin
  39.         rst = '0;
  40.         rready = '0;
  41.         wvalid = 0;
  42.         fifo_data_in = 16'd0;
  43.         #20000;
  44.         //填充FIFO
  45.         rst = 1;
  46.         wvalid = 1;
  47.         fifo_data_in = 16'h1111;
  48.         #20000;
  49.         fifo_data_in = 16'h2222;
  50.         #20000;
  51.         fifo_data_in = 16'h3333;
  52.         #20000;
  53.         fifo_data_in = 16'h4444;
  54.         #20000;
  55.         fifo_data_in = 16'h5555;
  56.         #20000;
  57.         fifo_data_in = 16'h6666;
  58.         #20000;
  59.         fifo_data_in = 16'h7777;
  60.         #20000;
  61.         fifo_data_in = 16'h8888;
  62.         #20000;
  63.         fifo_data_in = 16'h9999;
  64.         #20000;
  65.         fifo_data_in = 16'haaaa;
  66.         #20000;
  67.         fifo_data_in = 16'hbbbb;
  68.         #20000;
  69.         fifo_data_in = 16'hcccc;
  70.         #20000;
  73. <details>
  74. <summary>英文:</summary>
  76. I have been working on a FIFO for SystemVerilog.  The first simulations turned out good.  However, upon expanding the simulation to try to bring it to its limit and account for corner cases, I have encountered a few issues. Although I have been able to solve most of them there is one that I have not been able to solve.

//This fifo implements a Circular Buffer topology
//Note: The way the fifo is defined it is imposible to have a depth of 1
//This is because the pointers will always be on the same position
//The fifo is therefore always "empty"
module i2s_fifo #(
parameter WIDTH = 16,
parameter DEPTH = 10
)(
input logic clk_i,
input logic rst_ni,

  1. //Write Comunication Signals
  2. output logic wready,
  3. input logic wvalid,
  4. input logic [WIDTH-1:0] fifo_data_in,
  5. //Read Comunication Signals
  6. input logic rready,
  7. output logic rvalid,
  8. output logic [WIDTH-1:0] fifo_data_out,
  9. //Debuging
  10. output logic [$clog2(DEPTH)-1:0]wptr_tb,
  11. output logic [$clog2(DEPTH)-1:0] rptr_tb

);
//This returns how many bits are needed to add and adress of X size
//For example. $clog2(7) = 3. We need three bits to access a memory of 7 values.
//Basically converts from an interger to bits
localparam int unsigned byte_depth = $clog2(DEPTH);

  1. //Pointers
  2. logic [byte_depth-1:0] fifo_rptr, fifo_wptr; 
  3. assign wptr_tb = fifo_wptr;
  4. assign rptr_tb = fifo_rptr;
  5. //We cannot read if the FIFO is empty
  6. //We cannot write if the FIFO is full
  7. logic fifo_empty;
  8. logic fifo_full;
  9. always_comb begin : fifo_state   
  10. if(fifo_rptr == fifo_wptr) begin
  11. assign fifo_empty = 1&#39;b1;
  12. end else begin
  13. assign fifo_empty = 1&#39;b0;
  14. end
  15. if(fifo_wptr == DEPTH)begin //Pointer is at the edge of fifo
  16. if (fifo_rptr == 0) begin 
  17. fifo_full &lt;= 1&#39;b1;
  18. end else begin
  19. fifo_full &lt;= 1&#39;b0;
  20. end
  21. end else if (fifo_wptr+1 == fifo_rptr)begin
  22. fifo_full &lt;= 1&#39;b1;
  23. end else begin
  24. fifo_full &lt;= 1&#39;b0;
  25. end
  26. end
  27. //Handshake
  28. logic revent, wevent;
  29. assign rvalid = !fifo_empty;
  30. assign revent = rvalid &amp; rready;
  31. assign wready = !fifo_full;
  32. assign wevent = wvalid &amp; wready;
  33. //INCREASE POINTER POSSITION
  34. always_ff @(posedge clk_i) begin
  35. if(!rst_ni)begin
  36. fifo_rptr &lt;= {(byte_depth){1&#39;b0}};
  37. end else if (revent) begin
  38. if (fifo_rptr == DEPTH) begin
  39. fifo_rptr &lt;= {(byte_depth){1&#39;b0}};
  40. end else begin
  41. fifo_rptr &lt;= fifo_rptr+1;
  42. end
  43. end
  44. end
  45. always_ff @(posedge clk_i) begin
  46. if(!rst_ni)begin
  47. fifo_wptr &lt;= {(byte_depth){1&#39;b0}};
  48. end else if (wevent) begin
  49. if (fifo_wptr == DEPTH) begin
  50. fifo_wptr &lt;= {(byte_depth){1&#39;b0}};
  51. end else begin
  52. fifo_wptr &lt;= fifo_wptr+1;
  53. end
  54. end
  55. end
  56. //Write and Save data
  57. //data_type  [rows][columns] array_name;
  58. logic [DEPTH-1:0] [(WIDTH-1):0] fifo_storage;
  59. always_ff @(posedge clk_i)begin
  60. if(wevent) begin
  61. //This acces the row dictated by the pointer
  62. fifo_storage[fifo_wptr] &lt;= fifo_data_in;
  63. end
  64. end
  65. always_ff @(posedge clk_i)begin
  66. if(revent) begin
  67. fifo_data_out &lt;= fifo_storage[fifo_rptr];
  68. end
  69. end

endmodule

  2. And this is the testbench

module i2s_fifo_tb(

);
localparam WIDTH = 16;
localparam DEPTH = 10;
logic clk;
logic rst;
logic wready;
logic wvalid;
logic [WIDTH-1:0]fifo_data_in;
logic rready;
logic rvalid;
logic [WIDTH-1:0]fifo_data_out;
logic [$clog2(DEPTH)-1:0]rptr_tb;
logic [$clog2(DEPTH)-1:0]wptr_tb;
i2s_fifo #(
.WIDTH(16),
.DEPTH(10)
)UUT(
.clk_i(clk),
.rst_ni(rst),
.wready,
.wvalid,
.fifo_data_in,
.fifo_data_out,
.rready,
.rvalid,
.rptr_tb,
.wptr_tb
);
always begin
clk = '1;
#10000;
clk = '0;
#10000;
end

  1. initial begin
  2. rst = &#39;0;
  3. rready = &#39;0;
  4. wvalid = 0;
  5. fifo_data_in = 16&#39;d0;
  6. #20000;
  7. //Fill FIFO
  8. rst = 1;
  9. wvalid = 1;
  10. fifo_data_in = 16&#39;h1111;
  11. #20000;
  12. fifo_data_in = 16&#39;h2222;
  13. #20000;
  14. fifo_data_in = 16&#39;h3333;
  15. #20000;
  16. fifo_data_in = 16&#39;h4444;
  17. #20000;
  18. fifo_data_in = 16&#39;h5555;
  19. #20000;
  20. fifo_data_in = 16&#39;h6666;
  21. #20000;
  22. fifo_data_in = 16&#39;h7777;
  23. #20000;
  24. fifo_data_in = 16&#39;h8888;
  25. #20000;
  26. fifo_data_in = 16&#39;h9999;
  27. #20000;
  28. fifo_data_in = 16&#39;haaaa;
  29. #20000;
  30. fifo_data_in = 16&#39;hbbbb;
  31. #20000;
  32. fifo_data_in = 16&#39;hcccc;
  33. #20000;
  34. //Read FIFO
  35. wvalid = &#39;0;
  36. rready = &#39;1;
  37. #100000;
  38. //Pause Reading
  39. rready= 0;
  40. #100000;
  41. //Resume Reading
  42. rready = 1;
  43. #160000;
  44. //Check correct writing
  45. rready = 0;
  46. fifo_data_in = 16&#39;h1111;
  47. #20000;
  48. fifo_data_in = 16&#39;h2222;
  49. #20000;
  50. fifo_data_in = 16&#39;h3333;
  51. #20000;
  52. fifo_data_in = 16&#39;h4444;
  53. #20000;
  54. wvalid = 1;
  55. fifo_data_in = 16&#39;h5555;
  56. #20000;
  57. fifo_data_in = 16&#39;h6666;
  58. #20000;
  59. fifo_data_in = 16&#39;h7777;
  60. #20000;
  61. wvalid = 0;
  62. rready = 1;
  63. #80000;
  64. //Multiple Writing and reading
  65. rready = 0;
  66. wvalid = 1;
  67. fifo_data_in = 16&#39;h1111;
  68. #20000;
  69. fifo_data_in = 16&#39;h2222;
  70. #20000;
  71. fifo_data_in = 16&#39;h3333;
  72. #20000;
  73. rready = 1;
  74. fifo_data_in = 16&#39;h4444;
  75. #20000;
  76. fifo_data_in = 16&#39;h5555;
  77. #20000;
  78. fifo_data_in = 16&#39;h6666;
  79. #20000;
  80. wvalid = 0;
  81. //Fill it again, different point
  82. #60000;
  83. rready = 0;
  84. wvalid = 1;
  85. fifo_data_in = 16&#39;h1111;
  86. #20000
  87. fifo_data_in = 16&#39;h2222;
  88. #20000
  89. fifo_data_in = 16&#39;h3333;
  90. #20000
  91. fifo_data_in = 16&#39;h4444;
  92. #20000
  93. fifo_data_in = 16&#39;h5555;
  94. #20000
  95. fifo_data_in = 16&#39;h6666;
  96. #20000
  97. fifo_data_in = 16&#39;h7777;
  98. #20000
  99. fifo_data_in = 16&#39;h8888;
  100. #20000
  101. fifo_data_in = 16&#39;h9999;
  102. #20000
  103. fifo_data_in = 16&#39;haaaa;
  104. #20000
  105. fifo_data_in = 16&#39;hbbbb;
  106. #20000
  107. fifo_data_in = 16&#39;hcccc;
  108. #20000
  109. wvalid = 0;
  110. rready = 1;
  111. #600000
  112. $finish;
  113. end

endmodule

  1. Basically on the testbench I simply input a lot of data and check whether the fifo behaves accordingly. However. On the simulation I have observed that whenever the read pointer points to the zero position, the output is not define.
  2. At first I thought it may have been an issue with timing, that at the beginning of the simulation I simply did not write anything on the position zero and thus, when attempting to read int for the first time I have an undefined state. Thus, I decided to further the simulation. However, I have observed that any time the read pointer looks at the zero position, the state is undefined.
  3. My hypothesis is that there is some problem in this part
  1. //Write and Save data
  2. //data_type  [rows][columns] array_name;
  3. logic [DEPTH-1:0] [(WIDTH-1):0] fifo_storage;
  4. always_ff @(posedge clk_i)begin
  5. if(wevent) begin
  6. //This acces the row dictated by the pointer
  7. fifo_storage[fifo_wptr] &lt;= fifo_data_in;
  8. end
  9. end
  10. always_ff @(posedge clk_i)begin
  11. if(revent) begin
  12. fifo_data_out &lt;= fifo_storage[fifo_rptr];
  13. end
  14. end    
  1. namely that the vectors I&#39;m using to assign the data are wrong. But, I cannot pinpoint the  exact issue.
  2. I would appreciate some help.
  3. Here are two captures from the simulation:
  4. ![Simulation 1](https://i.stack.imgur.com/N1LkN.png)
  5. ![Simulation 2](https://i.stack.imgur.com/y1WVA.png)
  6. </details>
  7. # 答案1
  8. **得分**: 0
  9. 问题在于当您从FIFO中读取数据时，读指针会超出范围，导致从FIFO中读取数据时出现未知值。
  10. 您将FIFO的深度设置为10，这意味着您的读指针至少需要4位，并且您正确地声明了指针为`[3:0]`。然而，指针的一些可能值是非法的，即从10到15。只有从0到9的指针值是合法的。您的仿真波形清楚地显示，当`revent`为1时，指针达到值10（十六进制为`a`），这就是为什么`fifo_data_out`信号变为未知的原因。
  11. 请注意，输出信号是未知的，因为它在采样指针为10时更新了。
  12. 为了防止这种情况发生，您可以考虑将以下代码:
  13. ```verilog
  14. if (fifo_rptr == DEPTH) begin

更改为:

  1. if (fifo_rptr == (DEPTH-1)) begin

但是，您需要确保您的设计能正常工作。

英文:

The problem is that your read pointer goes out of range when you are reading from the FIFO, which results in unknown values when you read from the FIFO.

You set the FIFO DEPTH to 10, which means your read pointer needs at least 4 bits, and you properly declared the pointer as [3:0]. However, some of the possible values of the pointer are illegal, namely 10 through 15. Only pointer values from 0 to 9 are legal. Your simulation waveforms clearly show that the pointer reaches the value 10 (hexadecimal a) when revent is 1. This is why the fifo_data_out signals becomes unknown.

Note that the output signal is unknown because it was updated when the pointer was sampled as 10.

To prevent that from happening, you could consider changing:

  1.         if (fifo_rptr == DEPTH) begin

to:

  1.         if (fifo_rptr == (DEPTH-1)) begin

But, you need to make sure your design works properly.

huangapple
  • 本文由 发表于 2023年7月10日 19:04:04
  • 转载请务必保留本文链接：https://go.coder-hub.com/76653086.html
  • fifo
  • simulation
  • system-verilog
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