英文:
How do I disable assertions when signals are unknown?
问题
我正在尝试理解一个多路复用（MUX）示例模块中的一个断言。
我想检查SEL1、SEL2和SEL3信号之间的干扰，所以我声明如下：
always @(posedge CLOCK)
assert (SEL1 == 1 && SEL2 == 0 && SEL3 == 0);
我得到了关于SELx的一些断言失败。这是有道理的，我会修复它，但我不理解第一个失败：
xmsim: *E,ASRTST (./testbench.sv,31): (time 5 NS) Assertion T_MUX.MUX1.__assert_1 has failed
Starting 1st set of test vectors.
我认为这个失败不是来自于SELx，而是来自已知值。据我所知，已知值是不可避免的，即使在我们初始化系统之前，复位之前，系统的一些端口也有已知状态。
我如何正确地创建一个带有未知初始状态的断言检查器？
为了让你理解，我已经添加了 https://edaplayground.com/x/LLYS
module MUX
(
input wire CLOCK ,
input wire [3:0] IP1 ,
input wire [3:0] IP2 ,
input wire [3:0] IP3 ,
input wire SEL1 ,
input wire SEL2 ,
input wire SEL3 ,
output reg [3:0] MUX_OP
) ;
always @(posedge CLOCK)
if (SEL1 == 1)
MUX_OP <= IP1 ;
else if (SEL2 == 1)
MUX_OP <= IP2 ;
else if (SEL3 == 1)
MUX_OP <= IP3 ;
always @(posedge CLOCK)
assert (SEL1 == 1 && SEL2 == 0 && SEL3 == 0);
endmodule
英文:
I'm trying to understand a assertion in a MUX sample module.
I would like to check the interference between SEL1, SEL2 and SEL3 signals, So I declared as the below,
always @(posedge CLOCK)
assert (SEL1 == 1 && SEL2 ==0 && SEL3 == 0);
I got the some assertion fail about SELx. It make sense, and I will fix it, but I didn't understand the first fail:
xmsim: *E,ASRTST (./testbench.sv,31): (time 5 NS) Assertion T_MUX.MUX1.__assert_1 has failed
Starting 1st set of test vectors.
I think that fail does not come from SELx, it comes from known value.
As I know known. the unknown value is inevitable, even when we initiate the system, before reset, system's some ports have the known state.
How do I correctly make a assertion checker with unknown initial state?
For your understand I have added https://edaplayground.com/x/LLYS
module MUX
(
input wire CLOCK ,
input wire [3:0] IP1 ,
input wire [3:0] IP2 ,
input wire [3:0] IP3 ,
input wire SEL1 ,
input wire SEL2 ,
input wire SEL3 ,
output reg [3:0] MUX_OP
) ;
always @(posedge CLOCK)
if (SEL1 == 1)
MUX_OP <= IP1 ;
else if (SEL2 == 1)
MUX_OP <= IP2 ;
else if (SEL3 == 1)
MUX_OP <= IP3 ;
always @(posedge CLOCK)
assert (SEL1 == 1 && SEL2 ==0 && SEL3 == 0);
endmodule
答案1
得分: 2
在5纳秒时，所有3个SEL信号都是未知的(x)，因为MUX输入在7纳秒之前（第1个时钟边沿后的2纳秒）还没有确定的值。
如果您想在任何SEL信号具有未知值时禁用断言，您可以使用$isunknown系统函数：
always @(posedge CLOCK) begin
if (!$isunknown({SEL1, SEL2, SEL3})) begin
assert ( (SEL1 === 1) && (SEL2 === 0) && (SEL3 === 0) );
end
end
请参阅IEEE Std 1800-2017，第20.9节"Bit vector system functions"。
这将检查任何SEL信号是否为x或z。它会在仿真的整个持续时间内进行检查，而不仅仅是第1个时钟事件。
在更新后的EDA Playground上，在5纳秒时没有断言失败。
英文:
At time 5ns, all 3 SEL signals are unknown (x) because the MUX inputs are not driven with a known value until time 7ns (2ns after the 1st clock edge).
If you want to disable the assertion whenever any of the SEL signals has an unknown value, you can use the $isunknown system function:
always @(posedge CLOCK) begin
if (!$isunknown({SEL1, SEL2, SEL3})) begin
assert ( (SEL1 === 1) && (SEL2 === 0) && (SEL3 === 0) );
end
end
Refer to IEEE Std 1800-2017, section 20.9 Bit vector system functions.
This checks if any SEL signal is x or z. It checks for the duration of the simulation, not just the 1st clock event.
There is no assert fail at time 5ns on the updated EDA Playground.
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