英文:
non-blocking assignments with if statements
问题
关于Verilog如何解释这个代码块以及它在FPGA中的综合方式有点困惑。
...
data_reg[bit_count] <= rx;
bit_count <= bit_count + 1;
if (bit_count == 7) begin
bit_count <= 0;
end
...
问题是：如果 bit_count == 7，那么 data_reg[7] == rx 吗？还是 bit_count 在 data_reg[bit_count] 被赋值之前可能会改变，导致 data_reg[0] == rx？
英文:
A bit confused about how Verilog interprets this code block and how it is synthesized in FPGA.
...
data_reg[bit_count] <= rx;
bit_count <= bit_count + 1;
if (bit_count == 7) begin
bit_count <= 0;
end
...
The question is: if bit_count == 7 does data_reg[7] == rx or may bit_count change before data_reg[bit_count] gets assigned resulting in data_reg[0] == rx
答案1
得分: 1
如果这是顺序逻辑（always @(posedge clk)...），那么bit_count是其_旧_值或_当前_值。因此，如果它的当前值为7，分配将为8，但然后将被覆盖为0。在data_reg[bit_count]的左侧选择使用了bit_select的_旧_值。
如果这是组合逻辑，你不应该在块内部使用NBAs来操作变量。
英文:
If this is sequential logic (always @(posedge clk)...) Then bit_count is its old or current value. So if it's current value is 7, the assignment will be made to 8, but then it will be overridden to 0. The select on the LHS of data_reg[bit_count] uses the old value of bit_select.
If this is combinational logic, you should not be using NBAs to variables within the block.
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