英文:
Does anybody know how this code differentiates from normal D FF code?
问题
我正在进行验证项目并检查 DUT，我发现有些地方对我来说很不自然。
有大量的代码片段如下所示。
always @ (posedge clk) begin
if(rst)
q <= 0;
else if(q != d)
q <= d;
end
我认为这段代码与正常的 D 触发器代码完全相同，正常的代码如下：
always @ (posedge clk) begin
if(rst)
q <= 0;
else
q <= d;
end
有人能告诉我为什么代码要这样写吗？有什么特殊的含义吗？
我询问了几位同事关于这个问题，但没有得到满意的答案。
英文:
I am working on the verification project and inspecting DUT, I found something unnatural to me.
There are tons of code snippets like below.
always @ (posedge clk) begin
if(rst)
q <= 0;
else if(q != d)
q <= d;
end
I think this code works perfectly equal to normal D flip-flop code which is:
always @ (posedge clk) begin
if(rst)
q <= 0;
else
q <= d;
end
Can anybody tell me why the code is written like that? Is there any special meaning?
I asked several colleagues about this topic but I haven't got a satisfied answer.
答案1
得分: 0
关于RTL综合，它们在功能上是等效的。
但是，在模拟方面存在差异，如果q或d是未知的('x)。 q将保持在未知状态，直到有明确的复位。而如果d变为未知，q将保持在其当前状态。
我非常怀疑这不是该代码的原始作者的意图。更有可能是对D触发器建模方式的误解。
英文:
As far as RTL synthesis is concerned, they are functionally equivalent.
However, there is a difference in simulation if q or d is unknown('x). q remains in the unknown state until there is an explicit reset. And if d goes unknown, q remains in its current state.
I highly doubt this was the intent of the original author of this code. More likely it was a misunderstanding of how a D-FF should be modeled.
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