问题

Idea being using different axi_buses (Ex: axi_8_bus, axi_32_bus, axi_64_bus interfaces) depending on what WIDTH parameter is passed. I could write with axi_8_bus, axi_32_bus, axi_64_bus instances explicitly hardcoded but I want it to be dynamic instead.

It seems axi_``WIDTH``_bus isn't valid though.

Could anyone help please?

module top_assertion #(parameter WIDTH=8) (input rtl_signal);

axi_``WIDTH``_bus axi_bus;

assert property (@(posedge Clock) !$isunknown(axi_bus.valid);

endmodule

bind rtl_module top_assertion#(8) assertion(.*);

答案1

得分: 1

``` `` ``` 语法用于 `define` 编译器宏，而不是参数。

您可以使用带有 `case` 语句的 `generate` 结构，根据 `parameter` 值有条件地声明您需要的接口：

```verilog
module top_assertion #(parameter WIDTH=8) ();
    
    case (WIDTH)
        8 : axi_8_bus  axi_bus ();
        32: axi_32_bus axi_bus ();
        64: axi_64_bus axi_bus ();
    endcase
    
    //..(assertion checks on axi_bus)..
    
endmodule

请参考 IEEE Std 1800-2017，第 27.5 节 条件生成结构。generate 关键字是可选的。

<details>
<summary>英文:</summary>

The ``` `` ``` syntax is used with `define` compiler macros, not parameters.


You could use a `generate` construct with a `case` statement to conditionally declare the interface you need based on the `parameter` value:

    module top_assertion #(parameter WIDTH=8) ();
    
    case (WIDTH)
        8 : axi_8_bus  axi_bus ();
        32: axi_32_bus axi_bus ();
        64: axi_64_bus axi_bus ();
    endcase
    
    //..(assertion checks on axi_bus)..
    
    endmodule

Refer to IEEE Std 1800-2017, section 27.5 _Conditional generate constructs_.  The `generate` keyword is optional.

</details>