go
英文: Why uvm_driver class is not abstract class while other like class uvm_sequence also parameterize...
117system-verilog
uvm
go
英文: What is the meaning of numbers in UVM_INFO? 问题 以下是已翻译的部分： 以下消息来自通过运行 QuestaSim 模拟 dut 创建的转录文件。数字...
134system-verilog
uvm
go
英文: How do I get overridden transaction item in UVM driver? 问题 我正在尝试在UVM驱动程序中获取重写的事务项。我创建了一个UVM序列项类，...
104system-verilog
uvm
go
英文: How do I execute only targeted function from inherited uvm_test class? 问题 您可以在child_class_c的prin...
107system-verilog
uvm
go
英文: How do I start inherited uvm_test class? 问题 我试图使用.start()方法而不是uvm_config_db()来启动一个UVM测试类。 我已经注释掉...
121system-verilog
uvm
go
英文: Why does begin/end allow me to declare a variable partway through a SystemVerilog task? 问题 我试图在`...
122system-verilog
verilog
go
英文: If I use a blocking expression in the covergroup, do I need a sample directive from the previous...
173system-verilog
uvm
go
英文: EDA playground ERROR VCP5294 "Undefined package uvm_pkg" 问题 我正在尝试在EDA playground中编译一个小...
117system-verilog
uvm
117评论system-verilog
uvm