英文:
Create a pulse of a given signal
问题
我有一个名为sig的信号。这个信号可能在多个时钟周期内保持高电平。我想要创建一个脉冲，它应该在信号保持高电平的每个时钟周期内切换。
也就是说，每当我的信号sig从低电平变为高电平时，我都会获得一个脉冲。
具有挑战性的是，如果信号连续保持高电平，我该如何创建脉冲呢？
即使我的信号连续保持高电平三个时钟周期，我的脉冲也应该切换三次（从0到1，然后从1到0）。
module PULSE_GEN (input clk, input sig, input en, output wire pulse);
reg r1, r2, r3;
always @(posedge clk) begin
if (en)
begin
r1 = sig;
r2 = r1 ^ sig;
r3 = r1 & r2;
end
else
r3 = 1'b0;
end
assign pulse = r3;
endmodule
然而，我无法生成脉冲。波形按顺序显示了pulse、en、sig和clk。pulse始终保持低电平。
我创建了一个所需波形的示意图：
如图所示，sig在多个时钟周期内保持高电平。要求是脉冲应在时钟上升沿变为高电平，并在下一个时钟上升沿变为低电平。然后，当en条件为高电平（基本上是时间前进）时，脉冲再次变为高电平。如果en为低电平，则脉冲应为低电平。
英文:
I have a signal sig. This may remain high for multiple clock cycles. I want to create a pulse of it that should toggle for as many clock cycles for which the signal was high.
That is every time my signal sig goes from low to high, I will get a pulse of it.
The challenging thing is if the signal is high for multiple clk, how will I create a pulse of it?
Even though my signal is high for three consecutive clock cycles, my pulse should toggle three times (from 0 to 1 and 1 to 0).
module PULSE_GEN (input clk, input sig,input en,output wire pulse);
reg r1,r2,r3;
always @(posedge clk) begin
if(en)
begin
r1 =sig;
r2 = r1 ^ sig;
r3 = r1 & r2;
end
else
r3 = 1'b0;
end
assign pulse = r3;
endmodule
However, I am not able to generate the pulse. The waveform in the order shows pulse, en, sig and clk. pulse is always low.
I created a drawing of a desired waveform:
As the image shows ,sig is higher for multiple clock cycles.The requirement is that the pulse should become high on the posedge of clk and should become low on next posedge of the clk. And Again becomes high on next posedge as sig was high. This should happen only when en condition is high(which is basically Time advance).If en is low ,pulse should be low.
答案1
得分: 2
以下是翻译好的部分：
"The fact that you require pulse to rise with sig means you need to use Mealy style state machine; where the output is a function of its present state and current input. Mealy is fast, but is more susceptible to glitches and other limitation. I recommend searching: Mealy vs Moore. I also recommend searching about Verilog blocking vs non-blocking"
"你需要pulse随着sig上升的事实意味着你需要使用Mealy风格的状态机；其中输出是其当前状态和当前输入的函数。Mealy速度快，但更容易受到毛刺和其他限制的影响。我建议搜索：Mealy vs Moore。我还建议搜索关于Verilog阻塞与非阻塞的内容。"
"Your required behavior can be achieved with the below. I omitted the en as your question looks like homework. I will leave it to you to figure out."
"您所需的行为可以通过以下方式实现。我省略了en，因为您的问题看起来像是作业。我将让您自行解决。"
"assign pulse = !present_state && sig;"
"assign pulse = !present_state && sig;"
"always @(posedge clk) begin
present_state <= pulse && sig;
end"
"始终 @(posedge clk) begin
present_state <= pulse && sig;
end"
英文:
The fact that you require pulse to rise with sig means you need to use Mealy style state machine; where the output is a function of its present state and current input. Mealy is fast, but is more susceptible to glitches and other limitation. I recommend searching: Mealy vs Moore. I also recommend searching about Verilog blocking vs non-blocking
Your required behavior can be achieved with the below. I omitted the en as your question looks like homework. I will leave it to you to figure out.
assign pulse = !present_state && sig;
always @(posedge clk) begin
present_state <= pulse && sig;
end
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