英文:
Reset a simple counter
问题
I'm here to provide the translation as requested. Here's the translated text:
我正在尝试使用Verilog在Quartus Prime上编写一个简单的计数器，并使用Verilog编写的测试台在Questa FPGA ModelSim上进行测试。
我的计数器的目标是在时钟周期的上升沿计数到7，然后在达到7或低电平断言复位信号时重新从0开始。
我能够正确实现计数和在达到7后重新开始计数，但当复位信号被断言时，计数器却没有重新开始。
模块
// TFT_LCD_Driver 第二版本
module TFT_LCD_Driver(
input clk,
input rst_n,
output reg [3:0] cnt
);
initial cnt = 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 0;
if (cnt == 4'd7)
cnt <= 0;
else
cnt <= cnt + 4'd1;
end
endmodule
测试台
// TFT_LCD_Driver_tb
// spi driver 测试台
`define clk_period 20
module TFT_LCD_Driver_tb();
reg clk;
reg rst_n;
wire [3:0] cnt;
TFT_LCD_Driver tft(
.clk(clk),
.rst_n(rst_n),
.cnt(cnt)
);
initial begin
clk = 1'b1;
rst_n = 1'b1;
#30 rst_n = 1'b0;
#30 rst_n = 1'b1;
end
always #(`clk_period/2) clk = ~clk;
endmodule
这是不正确计数器的波形图
[](https://i.stack.imgur.com/2QQBS.png)
我期望看到当低电平断言复位信号被拉低时，计数器归零。然而，波形图显示它继续计数直到7，然后重新从0开始。我已经突出显示并标记了我期望重新开始的错误位置。
Please note that I've translated the text you provided. If you have any specific questions or need further assistance, feel free to ask.
英文:
I'm trying to write a simple counter using Verilog on Quartus Prime and a testbench in Verilog being tested with Questa FPGA modelSim.
The goal of my counter is to count up to 7 at positive edge of a clock cycle and wrap back to 0 after 7 or if the low assert reset signal is asserted.
I am getting the counting and the wrapping after 7 correct; however, the counter does not wrap back when the reset is asserted.
Module
// TFT_LCD_Driver Second Version
module TFT_LCD_Driver(
input clk,
input rst_n,
output reg [3:0] cnt
);
initial cnt = 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 0;
if (cnt == 4'd7)
cnt <= 0;
else
cnt <= cnt + 4'd1;
end
endmodule
TestBench
// TFT_LCD_Driver_tb
// spi driver test bench
`define clk_period 20
module TFT_LCD_Driver_tb();
reg clk;
reg rst_n;
wire [3:0] cnt;
TFT_LCD_Driver tft(
.clk(clk),
.rst_n(rst_n),
.cnt(cnt)
);
initial begin
clk = 1'b1;
rst_n = 1'b1;
#30 rst_n = 1'b0;
#30 rst_n = 1'b1;
end
always #(`clk_period/2) clk = ~clk;
endmodule
Here is waveform of the incorrect counter
I expect to see that the counter goes to 0 when the low assert reset signal is pulled low. However, the waveform shows that it continues to count until 7 and then wraps back to 0. I have highlighted and marked the incorrect spot where I expect the restart.
答案1
得分: 1
你的always块中有两个独立的if语句。第二个语句优先于第一个。在复位被断言之前，cnt的值为2。第一个赋值语句不会生效，但递增赋值语句会生效，将cnt设置为3。
你应该将：
if (cnt == 4'd7)
更改为：
else if (cnt == 4'd7)
英文:
You have 2 separate if statements in your always block. The 2nd one takes precedence over the 1st. Just before reset is asserted, cnt is 2. The 1st assignment does not take effect, but the increment assignment does take effect, setting cnt to 3.
You should change:
if (cnt == 4'd7)
to:
else if (cnt == 4'd7)
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 0;
else if (cnt == 4'd7)
cnt <= 0;
else
cnt <= cnt + 4'd1;
end
答案2
得分: 1
使用异步复位来建模一个计数器，通过在后面添加一个 else：
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 0;
else
if (cnt == 4'd7)
cnt <= 0;
else
cnt <= cnt + 4'd1;
end
英文:
Model a counter with asynchronous reset by adding an else to the post:
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 0;
else
if (cnt == 4'd7)
cnt <= 0;
else
cnt <= cnt + 4'd1;
end
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