Reference signal name from parent module

I want to reference the name of a signal that is on the input of my module.

For example, currently I write this.

sigref_checker
#(.reltol(0.0),
  .abstol(0.1),
  .startTime (111111ps),
  .stopTime(911111ps),
  ._signal("OUT1"),
  ._ref_signal("OUT2")
  )

  chk1 (
  .signal(OUT1),
  .ref_signal(OUT2),
  .enable_signal(1'b1)
  );

It would be nice if "._signal" and "._ref_signal" could be inferred internally in the chk1 module, so that my chk1 module prints:

> top.chk1.sig_ref_chk FAIL: OUT1 < OUT2-tol (1.666667 < 1.876363)

Instead of:

> top.chk1.sig_ref_chk FAIL: signal < ref_signal-tol (1.666667 <
> 1.876363)

I tried using macros inside the module, but I was not able to reference the parent signal name from within the module

It is possible to do this creating a C function using SystemVerilog's VPI.

int getParentName(char *user data) {
    vpiHandle system_h, arg_itr, in_h, , out_h, parent_handle;
    s_vpi_value out_s;
   // all this code just to get a handle to the function's argument
   // and without proper error checking
   sys_h = vpi_handle(vpiSysTfCall, NULL);
   arg_itr = vpi_iterate(vpiArgument, sys_h);
   in_h = vpi_scan(arg_itr);
   out_h = vpi_scan(arg_itr);
   // now get its parent net
   parent_h = vpi_get(vpiHighConn, in_h);
   // return the name of the net
   out_s.format = vpiStringVal;
   out_s.str = vpi_get_str(vpiName,parent_h);
   vpi_put_value(out_h,&out_s);
}

Inside your checker module you would call $getParentName(signal);

But it might be just easier to create a macro that instantiates your checker module

`define sigref_checker_inst(R,A,START,STOP,SIGNAL,REF) \
#(.reltol(R), \
  .abstol(A),\
  .startTime (START),\
  .stopTime(STOP),\
  ._signal(`"SIGNAL`"),\
  ._ref_signal(`"REF`")\
  )\
  chk1 (\
  .signal(SIGNAL),\
  .ref_signal(REF),\
  .enable_signal(1'b1)\
  );

 





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