条件case语句中的语法错误

huangapple
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英文:

Syntax error in conditional case statement

问题

以下是翻译好的内容：

我正在尝试制作一个控制器，但它一直给我以下错误：

  1. ./controller.v:46: 语法错误
  2. ./controller.v:47: 赋值语句的左值中存在语法错误。
  3. ./controller.v:46: 错误：无法理解的 case 表达式。
  4. ./controller.v:60: 语法错误
  5. ./controller.v:61: 赋值语句的左值中存在语法错误。
  6. ./controller.v:60: 错误：无法理解的 case 表达式。

我仍然不知道何时正确使用 begin 和 end，但这是我的代码：

  1. module controller (
  2.     input zero, clk, rst,
  3.     input [2:0] opcode, phase,
  4.     output reg sel, rd, ld_ir, halt, inc_pc, ld_ac, wr, ld_pc, data_e
  5. );
  8. always @(posedge clk or negedge rst)
  9.     case (phase)
  10.         3'd0: 
  11.         begin
  12.             sel = 1'b1;
  13.             rd = 1'b0;
  14.             ld_ir = 1'b0;
  15.             halt = 1'b0;
  16.             inc_pc = 1'b0;
  17.             ld_ac = 1'b0;
  18.             ld_pc = 1'b0;
  19.             wr = 1'b0;
  20.         end
  21.         3'd1: rd = 1'b1;
  22.         3'd2: ld_ir = 1'b1;
  23.         3'd3: ;
  24.         3'd4:
  25.         begin
  26.             sel = 1'b0;
  27.             rd = 1'b0;
  28.             ld_ir = 1'b0;
  29.             halt = (opcode == 3'b000)? 1'b1 : 1'b0;
  30.             inc_pc = 1'b1;
  31.             ld_ac = 1'b0;
  32.             ld_pc = 1'b0;
  33.             wr = 1'b0;
  34.             data_e = 1'b0;
  35.         end
  36.         3'd5:
  37.         begin
  38.             sel = 1'b0;
  39.             ld_ir = 1'b0;
  40.             halt = 1'b0;
  41.             inc_pc = 1'b1;
  42.             ld_ac = 1'b0;
  43.             ld_pc = 1'b0;
  44.             wr = 1'b0;
  45.             data_e = 1'b0;
  46.             case (opcode):
  47.                 3'b010, 3'b011, 3'b100, 3'b101: rd = 1'b1;
  48.                 default: rd = 1'b0;
  49.             endcase
  50.         end
  51.         3'd6:
  52.         begin
  53.             inc_pc = ((opcode == 3'b001) && zero ) ? 1'b1 : 1'b0;
  54.             ld_pc = (opcode == 3'b111) ? 1'b1 : 1'b0;
  55.             data_e = (opcode == 3'b110) ? 1'b1 : 1'b0;
  56.         end
  57.         default: 
  58.         begin
  59.             inc_pc = 1'b0;
  60.             case (opcode):
  61.                 3'b010, 3'b011, 3'b100, 3'b101: ld_ac = 1'b1;
  62.                 default: ld_ac = 0;
  63.             endcase
  64.             wr = (opcode == 3'b110) ? 1'b1 : 1'b0;
  65.         end
  66.     endcase
  67. endmodule

除了我的代码逻辑外，我想知道为什么会出现这些错误。

英文:

I'm trying to make a controller, but it keeps giving me the following error:

  1. ./controller.v:46: syntax error
  2. ./controller.v:47: Syntax in assignment statement l-value.
  3. ./controller.v:46: error: Incomprehensible case expression.
  4. ./controller.v:60: syntax error
  5. ./controller.v:61: Syntax in assignment statement l-value.
  6. ./controller.v:60: error: Incomprehensible case expression.

I still don't know when to use the begin and end correctly, but here's the code:

  1. module controller (
  2. input zero, clk, rst,
  3. input [2:0] opcode, phase,
  4. output reg sel, rd, ld_ir, halt, inc_pc, ld_ac, wr, ld_pc, data_e
  5. );
  6. always @(posedge clk or negedge rst)
  7. case (phase)
  8. 3'd0: 
  9. begin
  10. sel = 1'b1;
  11. rd = 1'b0;
  12. ld_ir = 1'b0;
  13. halt = 1'b0;
  14. inc_pc = 1'b0;
  15. ld_ac = 1'b0;
  16. ld_pc = 1'b0;
  17. wr = 1'b0;
  18. end
  19. 3'd1: rd = 1'b1;
  20. 3'd2: ld_ir = 1'b1;
  21. 3'd3: ;
  22. 3'd4:
  23. begin
  24. sel = 1'b0;
  25. rd = 1'b0;
  26. ld_ir = 1'b0;
  27. halt = (opcode == 3'b000)? 1'b1 : 1'b0;
  28. inc_pc = 1'b1;
  29. ld_ac = 1'b0;
  30. ld_pc = 1'b0;
  31. wr = 1'b0;
  32. data_e = 1'b0;
  33. end
  34. 3'd5:
  35. begin
  36. sel = 1'b0;
  37. ld_ir = 1'b0;
  38. halt = 1'b0;
  39. inc_pc = 1'b1;
  40. ld_ac = 1'b0;
  41. ld_pc = 1'b0;
  42. wr = 1'b0;
  43. data_e = 1'b0;
  44. case (opcode):
  45. 3'b010, 3'b011,3'b100, 3'b101: rd = 1'b1;
  46. default: rd = 1'b0;
  47. endcase
  48. end
  49. 3'd6:
  50. begin
  51. inc_pc = ((opcode == 3'b001) && zero ) ? 1'b1 : 1'b0;
  52. ld_pc = (opcode == 3'b111) ? 1'b1 : 1'b0;
  53. data_e = (opcode == 3'b110) ? 1'b1 : 1'b0;
  54. end
  55. default: 
  56. begin
  57. inc_pc = 1'b0;
  58. case (opcode):
  59. 3'b010, 3'b011,3'b100,3'b101: ld_ac = 1'b1;
  60. default: ld_ac = 0;
  61. endcase
  62. wr = (opcode == 3'b110) ? 1'b1 : 1'b0;
  63. end
  64. endcase
  65. endmodule

Apart from the logic of my code, I'd like to know why does it give me these errors.

答案1

得分: 0

问题在于你不应该在case行的末尾使用冒号。你只应该在case语句中的案例项后面使用冒号。例如，你的第一个case语句应该是这样的：

  1. case (opcode)
  2.     3'b010, 3'b011, 3'b100, 3'b101: rd = 1'b1;
  3.     default: rd = 1'b0;
  4. endcase

对于另一个case语句也是一样的。进行这些更改后，我不再出现语法错误。

你对begin/end的使用看起来是正确的。

英文:

The problem is that you should not use a colon at the end of the case lines. You should only use colons inside the case statement after the case items. For example, your 1st case statement should be:

  1. case (opcode)
  2. 3'b010, 3'b011,3'b100, 3'b101: rd = 1'b1;
  3. default: rd = 1'b0;
  4. endcase

The same applies to the other case statement. Making these changes, I no longer get syntax errors.

Your usage of begin/end looks correct.

huangapple
  • 本文由 发表于 2023年6月13日 01:01:15
  • 转载请务必保留本文链接：https://go.coder-hub.com/76458824.html
  • verilog
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