英文:
Syntax error in conditional case statement
问题
以下是翻译好的内容：
我正在尝试制作一个控制器，但它一直给我以下错误：
./controller.v:46: 语法错误
./controller.v:47: 赋值语句的左值中存在语法错误。
./controller.v:46: 错误：无法理解的 case 表达式。
./controller.v:60: 语法错误
./controller.v:61: 赋值语句的左值中存在语法错误。
./controller.v:60: 错误：无法理解的 case 表达式。
我仍然不知道何时正确使用 begin 和 end，但这是我的代码：
module controller (
input zero, clk, rst,
input [2:0] opcode, phase,
output reg sel, rd, ld_ir, halt, inc_pc, ld_ac, wr, ld_pc, data_e
);
always @(posedge clk or negedge rst)
case (phase)
3'd0:
begin
sel = 1'b1;
rd = 1'b0;
ld_ir = 1'b0;
halt = 1'b0;
inc_pc = 1'b0;
ld_ac = 1'b0;
ld_pc = 1'b0;
wr = 1'b0;
end
3'd1: rd = 1'b1;
3'd2: ld_ir = 1'b1;
3'd3: ;
3'd4:
begin
sel = 1'b0;
rd = 1'b0;
ld_ir = 1'b0;
halt = (opcode == 3'b000)? 1'b1 : 1'b0;
inc_pc = 1'b1;
ld_ac = 1'b0;
ld_pc = 1'b0;
wr = 1'b0;
data_e = 1'b0;
end
3'd5:
begin
sel = 1'b0;
ld_ir = 1'b0;
halt = 1'b0;
inc_pc = 1'b1;
ld_ac = 1'b0;
ld_pc = 1'b0;
wr = 1'b0;
data_e = 1'b0;
case (opcode):
3'b010, 3'b011, 3'b100, 3'b101: rd = 1'b1;
default: rd = 1'b0;
endcase
end
3'd6:
begin
inc_pc = ((opcode == 3'b001) && zero ) ? 1'b1 : 1'b0;
ld_pc = (opcode == 3'b111) ? 1'b1 : 1'b0;
data_e = (opcode == 3'b110) ? 1'b1 : 1'b0;
end
default:
begin
inc_pc = 1'b0;
case (opcode):
3'b010, 3'b011, 3'b100, 3'b101: ld_ac = 1'b1;
default: ld_ac = 0;
endcase
wr = (opcode == 3'b110) ? 1'b1 : 1'b0;
end
endcase
endmodule
除了我的代码逻辑外，我想知道为什么会出现这些错误。
英文:
I'm trying to make a controller, but it keeps giving me the following error:
./controller.v:46: syntax error
./controller.v:47: Syntax in assignment statement l-value.
./controller.v:46: error: Incomprehensible case expression.
./controller.v:60: syntax error
./controller.v:61: Syntax in assignment statement l-value.
./controller.v:60: error: Incomprehensible case expression.
I still don't know when to use the begin and end correctly, but here's the code:
module controller (
input zero, clk, rst,
input [2:0] opcode, phase,
output reg sel, rd, ld_ir, halt, inc_pc, ld_ac, wr, ld_pc, data_e
);
always @(posedge clk or negedge rst)
case (phase)
3'd0:
begin
sel = 1'b1;
rd = 1'b0;
ld_ir = 1'b0;
halt = 1'b0;
inc_pc = 1'b0;
ld_ac = 1'b0;
ld_pc = 1'b0;
wr = 1'b0;
end
3'd1: rd = 1'b1;
3'd2: ld_ir = 1'b1;
3'd3: ;
3'd4:
begin
sel = 1'b0;
rd = 1'b0;
ld_ir = 1'b0;
halt = (opcode == 3'b000)? 1'b1 : 1'b0;
inc_pc = 1'b1;
ld_ac = 1'b0;
ld_pc = 1'b0;
wr = 1'b0;
data_e = 1'b0;
end
3'd5:
begin
sel = 1'b0;
ld_ir = 1'b0;
halt = 1'b0;
inc_pc = 1'b1;
ld_ac = 1'b0;
ld_pc = 1'b0;
wr = 1'b0;
data_e = 1'b0;
case (opcode):
3'b010, 3'b011,3'b100, 3'b101: rd = 1'b1;
default: rd = 1'b0;
endcase
end
3'd6:
begin
inc_pc = ((opcode == 3'b001) && zero ) ? 1'b1 : 1'b0;
ld_pc = (opcode == 3'b111) ? 1'b1 : 1'b0;
data_e = (opcode == 3'b110) ? 1'b1 : 1'b0;
end
default:
begin
inc_pc = 1'b0;
case (opcode):
3'b010, 3'b011,3'b100,3'b101: ld_ac = 1'b1;
default: ld_ac = 0;
endcase
wr = (opcode == 3'b110) ? 1'b1 : 1'b0;
end
endcase
endmodule
Apart from the logic of my code, I'd like to know why does it give me these errors.
答案1
得分: 0
问题在于你不应该在case行的末尾使用冒号。你只应该在case语句中的案例项后面使用冒号。例如，你的第一个case语句应该是这样的：
case (opcode)
3'b010, 3'b011, 3'b100, 3'b101: rd = 1'b1;
default: rd = 1'b0;
endcase
对于另一个case语句也是一样的。进行这些更改后，我不再出现语法错误。
你对begin/end的使用看起来是正确的。
英文:
The problem is that you should not use a colon at the end of the case lines. You should only use colons inside the case statement after the case items. For example, your 1st case statement should be:
case (opcode)
3'b010, 3'b011,3'b100, 3'b101: rd = 1'b1;
default: rd = 1'b0;
endcase
The same applies to the other case statement. Making these changes, I no longer get syntax errors.
Your usage of begin/end looks correct.
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