"How to resolve 'unconnected port' and 'unused sequential element' warnings in Vivado synthesis for I2S Top module?

When synthesizing the above code in vivado, the following warning appears.

[Synth 8-3332] Sequential element (\i2s_rx/rx_right_reg[15] ) is unused and will be removed from module i2s_top.

[Synth 8-3331] design i2s_top has unconnected port i_tx_left_chan[15]
.
.
.
[Synth 8-3331] design i2s_top has unconnected port i_tx_left_chan[0]

[Synth 8-3331] design i2s_top has unconnected port i_tx_right_chan[15]
.
.
.
[Synth 8-3331] design i2s_top has unconnected port i_tx_right_chan[0]

How should I solve it?

Also, I am studying SOC RTL and I have to do synthesis, but I didn't say lib separately. Then, can I just do vivado synthesis? Should I do synthesis with any existing lib as a design compiler?

module i2s_top #(
    parameter AUDIO_DW = 16
)(
    input i_tx_sclk,
    input i_rst_n,
    input [AUDIO_DW-1:0] i_tx_prescaler,
    input [AUDIO_DW-1:0] i_tx_left_chan,
    input [AUDIO_DW-1:0] i_tx_right_chan,

    output [AUDIO_DW-1:0] o_rx_left_chan,
    output [AUDIO_DW-1:0] o_rx_right_chan
);

wire w_sclk;
wire w_lrclk;
wire w_sdata;

i2s_tx #(
    .AUDIO_DW(AUDIO_DW)
) i2s_tx (
    .i_tx_sclk(i_tx_sclk),
    .i_tx_rst_n(i_rst_n),
    .i_tx_prescaler(i_tx_prescaler),
    
    .o_tx_sclk(w_sclk),
    .o_tx_lrclk(w_lrclk),
    .o_tx_sdata(w_sdata),
    
    .i_tx_left_chan(i_tx_left_chan),
    .i_tx_right_chan(i_tx_right_chan)
);

i2s_rx #(
    .AUDIO_DW(AUDIO_DW)
) i2s_rx (
    .i_rx_sclk(w_sclk),
    .i_rx_rst_n(i_rst_n),
    .i_rx_lrclk(w_lrclk),
    .i_rx_sdata(w_sdata),
    .o_rx_left_chan(o_rx_left_chan),
    .o_rx_right_chan(o_rx_right_chan)
);

endmodule

module i2s_tx #(
    parameter AUDIO_DW = 16
)(
    input i_tx_sclk,
    input [AUDIO_DW-1:0] i_tx_prescaler,
    input i_tx_rst_n,
    
    output wire o_tx_sclk,
    output reg o_tx_lrclk = 0,
    output reg o_tx_sdata = 0,

    input [AUDIO_DW-1:0] i_tx_left_chan,
    input [AUDIO_DW-1:0] i_tx_right_chan
);

reg [AUDIO_DW-1:0] tx_bit_cnt = 1;
reg [AUDIO_DW-1:0] tx_left = 0;
reg [AUDIO_DW-1:0] tx_right = 0;

assign o_tx_sclk = i_tx_sclk;

always @(negedge i_tx_sclk or negedge i_tx_rst_n) begin
    if (!i_tx_rst_n) begin
        tx_bit_cnt = 1;
    end else if (tx_bit_cnt >= i_tx_prescaler) begin
        tx_bit_cnt <= 1;
    end else begin
        tx_bit_cnt <= tx_bit_cnt + 1;
    end

    if (!i_tx_rst_n) begin
        tx_left = 0;
        tx_right = 0;
    end else if (tx_bit_cnt == i_tx_prescaler && o_tx_lrclk) begin
        tx_left <= i_tx_left_chan;
        tx_right <= i_tx_right_chan;
    end
                
    o_tx_lrclk <= (tx_bit_cnt == i_tx_prescaler) ? ~o_tx_lrclk : o_tx_lrclk;
    
    o_tx_sdata <= o_tx_lrclk ? tx_right[AUDIO_DW - tx_bit_cnt] : tx_left[AUDIO_DW - tx_bit_cnt];
    
end

endmodule

module i2s_rx #(
    parameter AUDIO_DW = 16
)(
    input i_rx_sclk,
    input i_rx_rst_n,
    input i_rx_lrclk,
    input i_rx_sdata,

    output reg [AUDIO_DW-1:0] o_rx_left_chan = 0,
    output reg [AUDIO_DW-1:0] o_rx_right_chan = 0
);

reg [AUDIO_DW-1:0] rx_left = 0;
reg [AUDIO_DW-1:0] rx_right = 0;
reg rx_lrclk_r = 0;
wire rx_lrclk_nedge;

assign rx_lrclk_nedge = !i_rx_lrclk & rx_lrclk_r;

always @(posedge i_rx_sclk or negedge i_rx_rst_n)
        if (!i_rx_rst_n)
                rx_lrclk_r <= 0;
        else
                rx_lrclk_r <= i_rx_lrclk;

always @(posedge i_rx_sclk or negedge i_rx_rst_n)
        if (!i_rx_rst_n) begin
                rx_right <= 0;
                rx_left <= 0;
        end else if (rx_lrclk_r) begin
                rx_right <= {rx_right[AUDIO_DW-2:0], i_rx_sdata};
        end else 
                rx_left <= {rx_left[AUDIO_DW-2:0], i_rx_sdata};

always @(posedge i_rx_sclk or negedge i_rx_rst_n)
        if (!i_rx_rst_n) begin
                o_rx_left_chan <= 0;
                o_rx_right_chan <= 0;
        end else if (rx_lrclk_nedge) begin
                o_rx_left_chan <= rx_left;
                o_rx_right_chan <= {rx_right[AUDIO_DW-2:0], i_rx_sdata};
end

endmodule

synthesis Schematic
enter image description here

RTL Schematic
enter image description here

To resolve the "unconnected port" warning, you need to make sure that all the ports of your modules are connected to some signal. In your I2S top module, the following ports are not connected to any signal:

• i_rst_n
• w_sclk
• w_lrclk
• w_sdata

Make sure that you connect these ports to some signal, either internally or externally.

To resolve the "unused sequential element" warning, you can try optimizing your design. This warning typically indicates that there are registers that are not being used in your design, which can increase the resource utilization and timing complexity. You can try removing or optimizing these registers to improve your design.

Regarding your question about the library, Vivado synthesis uses the default library provided by Xilinx. However, if you have your own library with custom cells, you can specify it in Vivado by adding it to the library search path. To add a custom library, go to Project Settings > Verilog HDL Synthesis > Libraries and add the path to your library. If you didn't define any custom cells in your code, you don't need to worry about this and you can just use the default library.