在SystemVerilog中,可以将生成块放置在静态函数中吗?

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英文:

In SystemVerilog Is it possible to place a generate block in a static function?

问题

我正在使用虚拟类+静态函数来在SystemVerilog中实现参数化函数。这运行良好。但是,我现在正在尝试使函数的实现取决于参数值。例如:

virtual class C#(integer A);
    static function logic func(input a, input b);
        generate
            if (A == 1) begin
                return a & b;
            end
            else if (A == 2) begin
                return a ^ b;
            end
            else begin
                $error("Invalid parameter value.");
            end
        endgenerate
    endfunction
endclass

QuestaSim 报错:"near "generate": 语法错误,未预料到的 generate。"

这是否为非法语法?是否有实现上述功能的方法?

请注意,这是一个编造的示例,因为我不能分享我正在使用的实际代码,但它应该说明问题。
英文:

I'm using a virtual class + static function to implement parameterized functions in SystemVerilog. This works well. However, I'm now trying to make the function implementation conditional on the parameter values. For example:

virtual class C#(integer A);
    static function logic func(input a, input b);
        generate
            if (A == 1) begin
                return a & b;
            end
            else if (A == 2) begin
                return a ^ b;
            end
            else begin
                $error("Invalid parameter value.");
            end
        endgenerate
    endfunction
endclass

QuestaSim complains with "near "generate": syntax error, unexpected generate."

Is this illegal syntax? Is there any way to achieve the functionality above?

Please note that this is a contrived example, as I can't share the actual code I'm using, but it should illustrate the issue.

答案1

得分: 1

你不能将 generate 结构放在类定义内部。但在你的示例中,这是不必要的。你只需移除 generate/endgenerate 关键字,生成条件变为过程条件。

英文:

You cannot put a generate construct inside a class definition. But in your example, there is no need to. You can simply remove the generate/endgenerate keywords and the generate-if becomes a procedural-if.

答案2

得分: 1

这张图支持 @dave_59 的回答。

在SystemVerilog中,可以将生成块放置在静态函数中吗?

发布它是因为它支持了回答,而且我发现它不止一次地有用。

来源:

what-goes-where-in-systemverilog

英文:

This chart supports the @dave_59 answer.

在SystemVerilog中,可以将生成块放置在静态函数中吗?

Posting it because its supports the answer and have have found it useful more than once.
Source:

what-goes-where-in-systemverilog

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  • 本文由 发表于 2023年3月21日 01:52:37
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