问题

我有一个测试台（testbench）SV任务，可以检查一个1位逻辑信号的频率，用于测量时钟、有效信号等的频率... 但是如何测量多位数据信号的频率，以获得样本变化速度的大致概念呢？

问题在于我不想关心信号的大小，但编译器却在意。有没有办法将一个未指定大小的逻辑信号传递到 SV 任务中呢？例如：

  task automatic chk_data_rate(
    ref int signal, 
    input time timeout,
    output real meas_freq
  );
    : : :
  endtask

  real f;
  logic [23:0] a;
  logic [7:0] b;
  logic [31:0] c;
  chk_data_rate(a, 1ms, f);  
  chk_data_rate(b, 1ms, f);
  chk_data_rate(c, 1ms, f);

这里的错误是：

xmelab: *E,TYCMPAT (test.sv,1769|38): 引用形式和实际参数的数据类型不相等 
在实例 '$unit_0x78c03c36' 上 (期望与 'int' 兼容的数据类型，但找到 'packed 
array [23:0] of logic'）。

我可以将 int 更改为与 'a' 相同的类型，但我无法使其通用化...

我可以先将要分析的每个信号转换为单个位，然后再使用现有的任务，但这似乎很繁琐...

  task automatic chk_data_rate(
    ref int signal, 
    input time timeout,
    output real meas_freq
  );
    : : :
  endtask

  real f;
  logic [23:0] a;
  logic [7:0] b;
  logic [31:0] c;
  chk_data_rate(a, 1ms, f);  
  chk_data_rate(b, 1ms, f);
  chk_data_rate(c, 1ms, f);

答案1

得分: 1

以下是翻译好的部分：

> I don't want to care about the signal size but the compiler does.
"我不想关心信号大小，但编译器却关心。"

The following accepts a vector from 0 - 128 bits
"以下接受一个长度为 0 到 128 位的向量"

module tb ();
"模块 tb();"

task automatic chk_data_rate(
ref logic [127 : 0] my_signal,
input time timeout,
output real meas_freq
);
"任务自动检查数据速率(
引用 logic [127 : 0] my_signal,
输入时间 timeout,
输出实数 meas_freq
);"

$display("my_signal = %h",my_signal);
"$display("my_signal = %h",my_signal);"

endtask
"endtask"

real f;
"实数 f;"

logic [23:0] a;
"逻辑 [23:0] a;"

logic [7:0] b;
"逻辑 [7:0] b;"

logic [31:0] c;
"逻辑 [31:0] c;"

logic [127 : 0] a_stub;
"逻辑 [127 : 0] a_stub;"

logic [127 : 0] b_stub;
"逻辑 [127 : 0] b_stub;"

logic [127 : 0] c_stub;
"逻辑 [127 : 0] c_stub;"

always @* begin
"always @* begin"

a_stub = a;
"a_stub = a;"

b_stub = b;
"b_stub = b;"

c_stub = c;
"c_stub = c;"

end
"end"

initial begin
"initial begin"

a = 1;
"a = 1;"

b = 2;
"b = 2;"

c = 3;
"c = 3;"

#1;
"#1;"

chk_data_rate(a_stub, 1ms, f);
"chk_data_rate(a_stub, 1ms, f);"

chk_data_rate(b_stub, 1ms, f);
"chk_data_rate(b_stub, 1ms, f);"

chk_data_rate(c_stub, 1ms, f);
"chk_data_rate(c_stub, 1ms, f);"

$finish;
"$finish;"

end
"end"

endmodule
"endmodule"

Cadence, Mentor, Aldec and Synopsys produce:
"Cadence、Mentor、Aldec 和 Synopsys 产生："

my_signal = 00000000000000000000000000000001

"# my_signal = 00000000000000000000000000000001"

my_signal = 00000000000000000000000000000002

"# my_signal = 00000000000000000000000000000002"

my_signal = 00000000000000000000000000000003

"# my_signal = 00000000000000000000000000000003"

module tb ();
  
  task automatic chk_data_rate(
    ref logic [127 : 0] my_signal, 
    input time timeout,
    output real meas_freq
  );
    
    $display("my_signal = %h",my_signal);
    
  endtask

  real f;
  logic [23:0] a;
  logic [7:0]  b;
  logic [31:0] c;

  logic [127 : 0] a_stub;
  logic [127 : 0] b_stub;
  logic [127 : 0] c_stub;

  always @* begin
  a_stub = a;
  b_stub = b;
  c_stub = c;
  end

  initial begin
  a = 1;
  b = 2;
  c = 3;
  #1;
  chk_data_rate(a_stub, 1ms, f);  
  chk_data_rate(b_stub, 1ms, f);
  chk_data_rate(c_stub, 1ms, f);
  $finish;
  end
  
endmodule

# my_signal = 00000000000000000000000000000001
# my_signal = 00000000000000000000000000000002
# my_signal = 00000000000000000000000000000003

答案2

得分: 1

I'd suggest using parameterized classes to do it. Something like in the following example:

module mod;
  class abc #(size = 1);
    logic [size-1:0] data;
    function new();
    endfunction
    
    task monitor();
      $display("my size is %0d", size);
    endtask
  endclass

  abc #(24) a = new;
  abc #(8) b = new;
  abc #(63) c = new;
  
  initial begin
    a.monitor;
    b.monitor;
    c.monitor;
  end
endmodule

module mod;
  class abc #(size = 1);
    logic [size-1:0] data;
    function new();
    endfunction
    
    task monitor();
      $display("my size is %0d", size);
    endtask
  endclass

  abc #(24) a = new;
  abc #(8) b = new;
  abc #(63) c = new;
  
  initial begin
    a.monitor;
    b.monitor;
    c.monitor;
  end
endmodule