英文:
What is the difference between machine software interrupt and environment call from M-mode?
问题
如何触发机器软件中断？与M模式下的环境调用有何不同？
英文:
How to trigger a machine software interrupt?
Is it different from environment call from M-mode?
| Interrupt | Exception Code | Description |
|---|---|---|
| 1 | 0 | Reserved |
| 1 | 1 | Supervisor software interrupt |
| 1 | 2 | Reserved |
| 1 | 3 | Machine software interrupt |
| 1 | 4 | Reserved |
| 1 | 5 | Supervisor timer interrupt |
| 1 | 6 | Reserved |
| 1 | 7 | Machine timer interrupt |
| 1 | 8 | Reserved |
| 1 | 9 | Supervisor external interrupt |
| 1 | 10 | Reserved |
| 1 | 11 | Machine external interrupt |
| 1 | 12–15 | Reserved |
| 1 | ≥16 | Designated for platform use |
| 0 | 0 | Instruction address misaligned |
| 0 | 1 | Instruction access fault |
| 0 | 2 | Illegal instruction |
| 0 | 3 | Breakpoint |
| 0 | 4 | Load address misaligned |
| 0 | 5 | Load access fault |
| 0 | 6 | Store/AMO address misaligned |
| 0 | 7 | Store/AMO access fault |
| 0 | 8 | Environment call from U-mode |
| 0 | 9 | Environment call from S-mode |
| 0 | 10 | Reserved |
| 0 | 11 | Environment call from M-mode |
| 0 | 12 | Instruction page fault |
| 0 | 13 | Load page fault |
| 0 | 14 | Reserved |
| 0 | 15 | Store/AMO page fault |
| 0 | 16–23 | Reserved |
| 0 | 24–31 | Designated for custom use |
| 0 | 32–47 | Reserved |
| 0 | 48–63 | Designated for custom use |
| 0 | ≥64 | Reserved |
How to trigger a machine software interrupt? Is it different from environment call from M-mode?
答案1
得分: 1
经过阅读SiFive FU540-C000 Manual v1p4，我知道机器软件中断与M模式下的环境调用确实有所不同。
- 环境调用由
ecall指令触发。 - 软件中断通过写入特定的内存映射寄存器触发。
来自SiFive FU540-C000 Manual v1p4第66页
9.2 MSIP寄存器
通过写入内存映射控制寄存器msip生成机器模式软件中断。每个msip寄存器是一个32位宽的WARL寄存器，其中上31位连接到0。最不重要的位反映在mip CSR的MSIP位中。msip寄存器中的其他位被硬连线为零。复位时，每个msip寄存器被清零。
软件中断在多核系统中的处理器间通信中非常有用，因为处理器可以写入彼此的msip位以产生处理器间中断。
英文:
After reading SiFive FU540-C000 Manual v1p4, I know that machine software interrupt is truly different from environment call from M-mode.
- Environment call is triggered by
ecallinstruction. - Software interrupt is triggered by wrtiring a specified memory-mapped register.
From SiFive FU540-C000 Manual v1p4 Page 66
> 9.2 MSIP Registers
> Machine-mode software interrupts are generated by writing to the memory-mapped control register msip. Each msip register is a 32-bit wide WARL register where the upper 31 bits are tied to 0. The least significant bit is reflected in the MSIP bit of the mip CSR. Other bits in the msip registers are hardwired to zero. On reset, each msip register is cleared to zero.
Software interrupts are most useful for interprocessor communication in multi-hart systems, as
harts may write each other’s msip bits to effect interprocessor interrupts.
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