英文:
dsPIC33EP256MC506 Uart TRMT not empty on interrupt
问题
以下是您要翻译的内容：
所以我正在使用dsPIC33EP256MC506，其中一个UART用于通信（9600,8,N,2）。我需要在Tx移位寄存器为空（TRMT = 1）时获得中断。通过将UTXSEL位设置为：
USTAbits.UTXISEL0 = 1;
USTAbits.UTXISEL1 = 0;
根据数据表，UxSTA位15、13 UTXISEL[1:0]：= 01
11 = 保留；不要使用
10 = 当字符传输到传输移位寄存器（TSR）并且作为结果，传输缓冲区变为空时中断。
01 = 当最后一个字符从传输移位寄存器中移出时中断；所有传输操作都已完成。
00 = 当字符传输到传输移位寄存器时中断（这意味着传输缓冲区中至少有一个字符打开）。
我知道它说“...当最后一个字符从...移出时...”，这意味着移位寄存器不为空。另一方面，它还说“...所有传输操作都已完成。”，这意味着移位寄存器应该为空。
然而，当中断触发时，FIFO为空，TRMT = 0。因此，仍然存在正在进行的移位操作。
TRMT：传输移位寄存器为空位（只读）
1 = 传输移位寄存器为空且传输缓冲区为空（上次传输已完成）
0 = 传输移位寄存器不为空，传输正在进行或排队中
在我的示波器上，中断似乎在停止位之间触发。
我看不出模式10和01之间有实际区别，两者都在移位寄存器中有数据时触发中断。请问有人可以解释/确认这是否是又一个Microchip的错误，或者模式10和01之间的实际区别是什么。
我真正需要知道的是最后一个停止位何时离开移位寄存器。
神秘之谜已解开
这是一个硅芯片错误，并在勘误表中提到。
当使用UTXISEL<1:0> = 01（中断当最后一个字符从传输移位寄存器中移出时），并且最后一个字符正在通过传输移位寄存器（TSR）移出时，传输（TX）中断可能会在最后一位移出之前发生。
英文:
So I'm using the dsPIC33EP256MC506 and one of its UART for communication (9600,8,N,2). I need to get an interrupt when the Tx shift register is empty (TRMT = 1). By setting the UTXSEL bits to:
USTAbits.UTXISEL0 = 1;
USTAbits.UTXISEL1 = 0;
According to the data sheet UxSTA bit 15,13 UTXISEL[1:0]: = 01
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result,
the transmit buffer becomes empty.
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed.
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there
is at least one character open in the transmit buffer).
I know it says "...when the last character is shifted out..." which implies that the shift register isn't empty. On the other hand it also says "...all transmit operations are completed." which implies that the shift register should be empty.
However when the interrupt trig, the FIFO is empty and the TRMT = 0. So there is still a shift operation in progress.
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
On my Oscilloscope it looks like the interrupt is triggered somewhere among the stop bits.
I fail to see a practical difference between mode 10 and 01, both gives interrupt when there is data in the shift register.
Can some one explain/confirm if this is yet another Microchip bug or what the practical difference is between mode 10 and 01.
What I really need is to know when the last stop bit has left the shift register.
MYSTERY SOLVED
It is a silicon bug and it's mentioned in the errata.
> When using UTXISEL<1:0> = 01 (interrupt when last character is shifted
> out of the Transmit Shift Register) and the final character is being
> shifted out through the Transmit Shift Register (TSR), the Transmit
> (TX) interrupt may occur before the final bit is shifted out.
答案1
得分: 0
我猜你可以将它视为一个两字节的缓冲区。
第一个字节是“传输缓冲区”，软件可以直接写入它（当它为空时）。第二个字节是移位寄存器，它从“传输缓冲区”中读取字节并将它们移动到线上。
“10”模式告诉你传输缓冲区现在是空的（你可以写入其他内容），因为一个字节刚刚被移到移位寄存器中。
“01”模式告诉你移位寄存器何时被清空，即整个字节现在位于线上。
当停止位正在线上被传输时，你可以收到中断，因为停止位不是移位寄存器中的数据的一部分。所有数据都已经移出。停止位对于MCU来说是“元数据”。
感觉我只是用不同的话重新陈述了你说的话。但对我来说是有意义的，所以不确定哪一部分让你感到困惑。
英文:
I guess you can consider it as a two-byte buffer.
The first byte is the "transmit buffer", which software can write directly to (when it is empty). The second byte is the shift register, which reads bytes from the "transmit buffer" and shifts them onto the wire.
10 mode tells you the transmit buffer is now empty (and you can write something else into it) since a byte just got moved into the shift register.
01 mode tells you when the shift register got emptied, i.e. the entire byte is now on the wire.
You can get an interrupt while the stop bit is being driven on the wire, because the stop bit is not part of the data in the shift register. All the data has been shifted out. The stop bit is "meta-data" as far as the MCU is concerned.
It feels like I just re-stated what you said in different words. But it makes sense to me, so not sure which part has confused you.
答案2
得分: 0
I know it says "...当最后一个字符被移出..." which implies that the shift register isn't empty. On the other hand it also says "...所有发送操作已完成..." which implies that the shift register should be empty.
However when the interrupt trig, the FIFO is empty and the TRMT = 0. So there is still a shift operation in progress.
I fail to see a practical difference between mode 10 and 01, both gives interrupt when there is data in the shift register. In mode 01 the interrupt occurs when the shift register is empty. In mode 10 it occurs then the FIFO is empty.
You would use use mode 10b to indicate FIFO empty and allow you to load the buffer to stream data without inter-character gaps.
You might use mode 01b to indicate all data has been transmitted before disabling the UART or entering a low power mode or issuing a software reset for example. Or if you needed precise timing/synchronisation between character output and some other I/O event - for example you might be communicating with some device with a chip-select control that needs to be held up until completion.
In most cases you would want to use mode 10b, load the FIFO until UTXBF, then repeat on a mode 10b interrupt.
英文:
>I know it says "...when the last character is shifted out..." which implies that the shift register isn't empty. On the other hand it also says "...all transmit operations are completed." which implies that the shift register should be empty.
It seems this is a comprehension issue. What makes you think that "when the last character is shifted out" implies the register is not empty? It means exactly that - you even noted that with your oscilloscope.
> However when the interrupt trig, the FIFO is empty and the TRMT = 0. So there is still a shift operation in progress.
That is true on mode 10 only.
> I fail to see a practical difference between mode 10 and 01, both gives interrupt when there is data in the shift register.
In mode 01 the interrupt occurs when teh shift register is empty. In mode 10 it occurs then the FIFO is empty
You would use use mode 10b to indicate FIFO empty and allow you to load the buffer to stream data without inter-character gaps.
You might use mode 01b to indicate all data has been transmitted before disabling the UART or entering a low power mode or issuing a software reset for example. Or if you needed precise timing/synchronisation between character output and some other I/O event - for example you might be communicating with some device with a chip-select control that needs to be held up until completion.
In most cases you would want to use mode 10b, load the FIFO until UTXBF, then repeat on a mode 10b interrupt.
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