Fatal: (vsim-3807) Types do not match between component and entity for port "out1" Without Identifiable Cause

I've read all the other questions asked with the same issue, but none of them were helpful. Either not enough information was given and so the question remained unanswered, or the answers didn't apply to my case. I'm getting this error (as shown below) and I can't figure out what is causing it.

# vsim -novopt -c -t 1ps -L fiftyfivenm -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.demultiplexer_vhd_vec_tst 

# Start time: 19:44:15 on Apr 10,2023

# Loading std.standard

# Loading std.textio(body)

# Loading ieee.std_logic_1164(body)

# Loading work.demultiplexer_vhd_vec_tst(demultiplexer_arch)

# Loading ieee.vital_timing(body)

# Loading ieee.vital_primitives(body)

# Loading fiftyfivenm.fiftyfivenm_atom_pack(body)

# Loading fiftyfivenm.fiftyfivenm_components

# Loading work.demultiplexer(structure)

# ** Fatal: (vsim-3807) Types do not match between component and entity for port "out1".

# Time: 0 ps  Iteration: 0  Instance: /demultiplexer_vhd_vec_tst/i1 File: LabNine.vho Line: 39

# FATAL ERROR while loading design

# Error loading design

# End time: 19:44:15 on Apr 10,2023, Elapsed time: 0:00:00

# Errors: 1 Warnings: 0

Error

Here is the code in question:

ENTITY demultiplexer IS
	PORT (  out1 : OUT BIT_VECTOR (0 TO 7); 
			out2 : OUT BIT_VECTOR (0 TO 7); 
			out3 : OUT BIT_VECTOR (0 TO 7); 
			CLR : OUT BIT; 
			inbus : IN BIT_VECTOR(0 TO 7); 
			S0 : IN BIT; S1 : IN BIT);
END demultiplexer;

ARCHITECTURE dataflow OF demultiplexer IS
BEGIN
process(S0, S1)
	BEGIN
		IF (S0 = '0') and (S1 = '0') THEN
			CLR <= '1';
		ELSIF (S0 = '1') and (S1 = '0') THEN
			out1(0) <= inbus(0);
			out1(1) <= inbus(1);
			out1(2) <= inbus(2);
			out1(3) <= inbus(3);
			out1(4) <= inbus(4);
			out1(5) <= inbus(5);
			out1(6) <= inbus(6);
			out1(7) <= inbus(7);
			CLR <= '0';
		ELSIF (S0 = '0') and (S1 = '1') THEN
			out2(0) <= inbus(0);
			out2(1) <= inbus(1);
			out2(2) <= inbus(2);
			out2(3) <= inbus(3);
			out2(4) <= inbus(4);
			out2(5) <= inbus(5);
			out2(6) <= inbus(6);
			out2(7) <= inbus(7);
			CLR <= '0';
		ELSIF (S0 = '1') and (S1 = '1') THEN
			out3(0) <= inbus(0);
			out3(1) <= inbus(1);
			out3(2) <= inbus(2);
			out3(3) <= inbus(3);
			out3(4) <= inbus(4);
			out3(5) <= inbus(5);
			out3(6) <= inbus(6);
			out3(7) <= inbus(7);
			CLR <= '0';
		END IF;
	END process;
END dataflow;

In the waveform file, the variables' transitions are set to occur every:

S0 = 50ns

S1 = 100ns

inbus[0] = 200ns

inbus[1] = 400ns

inbus[2] = 800ns

inbus[3] = 1600ns

inbus[4] = 3200ns

inbus[5] = 6400ns

inbus[6] = 12800ns

inbus[7] = 25600ns

And the end time is set to 51200ns

And here is the LabNine.vho file, with the line in question:

ARCHITECTURE structure OF demultiplexer IS

SIGNAL gnd : std_logic := '0';

SIGNAL vcc : std_logic := '1';

SIGNAL unknown : std_logic := 'X';

SIGNAL devoe : std_logic := '1';

SIGNAL devclrn : std_logic := '1';

SIGNAL devpor : std_logic := '1';

SIGNAL ww_devoe : std_logic;

SIGNAL ww_devclrn : std_logic;

SIGNAL ww_devpor : std_logic;

SIGNAL ww_out1 : std_logic_vector(0 TO 7);

SIGNAL ww_out2 : std_logic_vector(0 TO 7);

SIGNAL ww_out3 : std_logic_vector(0 TO 7);

SIGNAL ww_CLR : std_logic;

SIGNAL ww_inbus : std_logic_vector(0 TO 7);

SIGNAL ww_S0 : std_logic;

SIGNAL ww_S1 : std_logic;

SIGNAL \out1[7]~output_o\ : std_logic;

SIGNAL \out1[6]~output_o\ : std_logic;

SIGNAL \out1[5]~output_o\ : std_logic;

SIGNAL \out1[4]~output_o\ : std_logic;

SIGNAL \out1[3]~output_o\ : std_logic;

SIGNAL \out1[2]~output_o\ : std_logic;

SIGNAL \out1[1]~output_o\ : std_logic;

SIGNAL \out1[0]~output_o\ : std_logic;

SIGNAL \out2[7]~output_o\ : std_logic;

SIGNAL \out2[6]~output_o\ : std_logic;

SIGNAL \out2[5]~output_o\ : std_logic;

SIGNAL \out2[4]~output_o\ : std_logic;

SIGNAL \out2[3]~output_o\ : std_logic;

SIGNAL \out2[2]~output_o\ : std_logic;

SIGNAL \out2[1]~output_o\ : std_logic;

SIGNAL \out2[0]~output_o\ : std_logic;

SIGNAL \out3[7]~output_o\ : std_logic;

SIGNAL \out3[6]~output_o\ : std_logic;

SIGNAL \out3[5]~output_o\ : std_logic;

SIGNAL \out3[4]~output_o\ : std_logic;

SIGNAL \out3[3]~output_o\ : std_logic;

SIGNAL \out3[2]~output_o\ : std_logic;

SIGNAL \out3[1]~output_o\ : std_logic;

SIGNAL \out3[0]~output_o\ : std_logic;

...

Any and all help is appreciated! If you're curious about the lab names, the lab has already happened, and the demultiplexer worked perfectly during the physical demonstration with the DE10-Lite board. Which is why I'm even more perplexed at why it is having an issue now, for the simulation.

Despite not being used by the waveform simulator in any way, you have to have the pin assignments laid out (and done correctly) in order for the simulation to actually work.