Makefile variable printing empty despite definition structure

I am working on a C++ library where I am following the structure below:

ROOTDIR = ~/path/to/proj
BLDDIR = $(ROOTDIR)/build
INCDIR = $(ROOTDIR)/include
SRCDIR = $(ROOTDIR)/src
LIBSRCDIR = $(SRCDIR)/lib
TESTSRCDIR = $(SRCDIR)/test
OBJDIR = $(ROOTDIR)/obj
LIBOBJDIR = $(OBJDIR)/lib
TESTOBJDIR = $(OBJDIR)/test
LIBDIR = $(ROOTDIR)/lib
BINDIR = $(ROOTDIR)/bin

And the file definitions are:

MKFILE = $(BLDDIR)/Makefile
HDRFILES = $(wildcard $(INCDIR)/*.hpp)
LIBSRCFILES := $(wildcard $(LIBSRCDIR)/*.cpp)
TESTSRC = $(TESTSCRCDIR)/test.cpp
LIBOBJFILES := $(patsubst $(LIBSRCDIR)/%.cpp, $(LIBOBJDIR)/%.o, $(LIBSRCFILES))
TESTOBJ := $(TESTOBJDIR)/test.o
LIBFILE = $(LIBDIR)/$(NAME)-$(VERSION).a
TESTFILE = $(BINDIR)/test
ZIPFILE = $(ROOTDIR)/$(NAME).$(VERSION).zip

I have tested & confirmed that everything works, but for some reason $(TESTSRC) is printing empty even though Make is able to set $(TESTOBJ). I tried setting up the variable definitions in the hierarchy to ensure everything is generated in level, but that one variable remains empty.

EDIT 1:

• Make is finding all of the directories properly
• I have made sure that the file extension is correct
• The variable is not being overwritten

EDIT 2:
The specific error I"mg getting is:
make: *** No rule to make target /test.cpp', needed by ..../test.o

..../test.o is in the right directory & defined separately without being dependent on a patsubst like the libsrc.

Read carefully:

TESTSRCDIR = $(SRCDIR)/test
    ^^^

and:

TESTSRC = $(TESTSCRCDIR)/test.cpp
                ^^^