Include only specific targets from another makefile?

Suppose I have two adjacent directories A and B.
In A is makefile_a, and in B is makefile_b.

makefile_b does some preprocessing whose output is later used by the targets of makefile_a. So I would like to define certain targets in makefile_a to depend on targets in makefile_b.

Normally I would do this with, in makefile_a, the line include ../B/makefile_b, as described in make's documentation on include.
However, I don't want to pollute the namespace of makefile_a with all the targets defined in makefile_b; I only want to import the one target in question. For example, there are targets with identical names defined in both makefile_a and makefile_b which would clash. For that and other reasons I only want to import the one target in question, not all of them.

How can this be done? I don't see any way to do that explained in the documentation. I considered making a second makefile in B, something like makefile_b_export, to be included by both makefile_a and makefile_b, and contain only the targets that I wish to include in makefile_b, but that would be a hack and presents its own set of issues, like how do the exported targets depend on those defined in makefile_b without creating an import cycle.

Is there a proper way to handle this scenario using make? What do you suggest would be the cleanest way to handle this situation?

There is no way to include just "part" of a file, or just "some" targets.

You can either take the content that's shared in put it into a separate file such as shared_b.mk and then add include shared_b.mk to both the makefiles.

Or, you can use ifdef to skip including the non-shared content if a variable is set, then before you include makefile_b you can set that variable.

Or, instead of including the makefiles you can have makefile_a build the specific target(s) in makefile_b by having a rule that invokes make recursively in that subdirectory:

.PHONY: targ_b1 targ_b2
targ_b1 targ_b2:
        $(MAKE) -C ../b $@

or whatever.