如何将包含的Make文件分隔到不同的环境中?

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英文:

How to seperate included make files into different environments?

问题

基本上我有两个 makefiles:

一个位于根目录,包括所有子项目:

CXX="gcc"
CFLAGS="-I./include"

include subproject/make.mk

hello: hello.o subproject/test.o
$(CXX) -o hello hello.o subproject/test.o

hello.o: hello.c
$(CXX) $(CFLAGS) -o hello.o -c hello.c

我还有 subproject/make.mk

CFLAGS+="-Isubproject/include"

subproject/test.o: subproject/test.c
$(CXX) $(CFLAGS) -o subproject/hello.o -c subproject/test.c

如你所见,子 makefile 会添加到 CFLAGS,但我想在子 makefile 中仅在那里显示对 CFLAGS 的修改。是否有任何分离 makefiles 环境并仅传递一些变量的方法?还是必须使用单独的变量?

我尝试使用递归的 make,但这不可扩展,特别是如果我的子项目依赖于另一个。

英文:

Basically I have two makefiles:

One at root which includes all the sub projects:

CXX="gcc"
CFLAGS="-I./include"

include subproject/make.mk

hello: hello.o subproject/test.o
$(CXX) -o hello hello.o subproject/test.o

hello.o: hello.c
$(CXX) $(CFLAGS) -o hello.o -c hello.c

I also have subproject/make.mk:

CFLAGS+="-Isubproject/include"

subproject/test.o: subproject/test.c
$(CXX) $(CFLAGS) -o subproject/hello.o -c subproject/test.c

As you can see the sub makefile adds to CFLAGS, however I want the modification to CFLAGS there to only appear in that sub makefile. Is there any way to separate the makefiles environments and only pass some variables? Or do I have to use separate variables?

I tried using recursive make however that is not expandable especially if one of my subprojects depend on another.

答案1

得分: 0

没有办法修改全局变量,使其仅在某些目标上生效。

但是,你可以创建一个目标特定的变量

subproject/test.o: CFLAGS += -Isubproject/include
subproject/test.o: subproject/test.c
    $(CXX) $(CFLAGS) -o subproject/hello.o -c subproject/test.c

然而,你必须明确地为所有你想要的目标执行此操作,不能自动添加到所有包含文件中的目标。

在make中,包含操作发生在非常低的级别。就makefile解析器而言,它基本上就像你已经将所有makefile合并成一个大文件一样(类似于C/C++预处理器的工作方式)。解析器看不到一个文件在哪里结束,另一个文件在哪里开始。

英文:

There is no way to modify a global variable so it only is in effect for some targets.

But, you can create a target-specific variable:

subproject/test.o: CFLAGS += -Isubproject/include
subproject/test.o: subproject/test.c
        $(CXX) $(CFLAGS) -o subproject/hello.o -c subproject/test.c

However you have to do it for all the targets you want explicitly, there's no way to just automatically add it to all targets in an included file.

In make, inclusion happens at a very very low level. As far as the makefile parser is concerned it's essentially like you have combined all the makefiles into one big file (similar to how the C/C++ preprocessor works). The parser doesn't see where one file stops and another starts.

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  • 本文由 发表于 2023年7月7日 07:09:28
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