Multiplying two 64 bits numbers in RISC-V assembly

I was confused on how I would go about multiplying two 64 bits with each other in Risc-v assembly. I want to load numbers that are 64 bits, multiply them, and store it back in a variable and print the result.

From what I understand you have to load the variables into a register, use mul and mulh to store upper and lower and then store it back in the result variable. This is what I understand about the mul and mulh:

mul x12, x10, x11
mulh x13, x10, x11

I take the x10 and x11 and multiply them storing upper and lower bits. I was confused in how I would load the 64 bits into x10 and x11. I tried using ld x10, 0(number1) and doing the same with x11 but it doesn't give correct results when multiplying x10 and x11. how would I go about doing this in Risc-v

Mathematically speaking, a 64×64 multiplication results in a 128-bit answer with guaranteed no overflow (anything less risks overflow for some inputs).  This is called widening multiplication.

As Peter says, though, if you're going to limit your result back to 64 bits and assume no overflow, you can simplify the calculations.

If you're on a 32-bit machine, 64-bit values will occupy two registers.

For arithmetic, there's two operands, — so, a pair of registers for each operand, for a total of 4 registers just for the source operands.

For each 64-bit operand, need to load high order and low order.  It will be up to your storage format, but if you're using little endian as would be expected on RISC V, then the low order comes first and the high order 4 bytes further on, when stored in memory.  If you already have the values in registers, so much the better, just be clear about which is high order and which is low order.

RISC V has no double register loads (or stores) so, you get to pick register numbers, which could be, for example, x10,x11 for one pair or x11,x10 for the same pair, with reversed high/low order, totally up to you, but you certainly don't even need to use consecutive register numbers for the register pair (though that would be expected and reduce cognitive load for programmers).

You then need to multiply the two pairs as in long multiplication, which sums shorter multiplications to make the full answer.

Let's be aware then that on 32-bit machine, we have 32×32 => 64-bit answer.  So, we break down the 64×64 => 128 multiplication into several 32×32 => 64-bit answers to be summed with appropriate scaling.

Let's say that one 64-bit number is AB, with A the high order 32 bits and B the low order 32 bits, while the other is CD (similarly two 32-bit halves).

AB × CD =
(A &times; C << 64) + (A &times; D << 32) +
(B &times; C << 32) +
(B &times; D)

Each separate multiplication in the above requires a mul and mulh (mulhu if unsigned operands), producing 64-bit answers.&nbsp; These 64-bit answers (4 of them) need to be effectively shifted then summed (the shifting is either none, 32 or 64, so no actual shifting needed, just using the right registers in the right places).

The summing must take place with carry taken into account, so that adds a few more instructions, but they are simple.

A C compiler (e.g. godbolt) in the right configuration can show the basics, though since standard C doesn't support widening arithmetic, can't show the true 64&times;64 => 128 form, though there may be some compiler (e.g. gcc) extensions/builtins that support the widening forms.