makefile: escape character / expand variable differs with users

I have a makefile where a rule has below echo in a recipe :

@echo "DUPW $(VAR1).FILE*"

The value of variable VAR1 = DATA.SUBVOL

When running the make (on OSS, a Unix like OS) under user A it echoes it the way I want it :

DUPW $DATA.SUBVOL.FILE*

But when running the same make under user B it echoes :

DUPW \DATA.SUBVOL.FILE*

What causes above different behaviour between the 2 users ?

The diffent behaviour also occurs when I change the recipe as follows :

@echo "DUPW $$$(VAR1).DICT*"

But now user A echoes it incorrect :

DUPW $.SUBVOL.FILE*

and user B echoes it in the way I want it :

DUPW $DATA.SUBVOL.FILE*

Well, I'm not familiar with OSS, a Unix like OS so I don't know what make implementation is on it. If you run make --version does it tell you anything useful? There's certainly no make implementation I'm familiar with that will emit both those behaviors. Are you sure that both users are running the exact same make implementation?

Basically, the behavior of make for User B is correct according to the POSIX standard. A recipe line like this:

@echo "DUPW $(VAR1).FILE*"

will first expand the makefile variable $(VAR1) (in POSIX make, backslashes are not special in any way; they're just a character like any other character) and so if VAR1 has the value DATA.SUBVOL the result of expansion will be:

@echo "DUPW \DATA.SUBVOL.FILE*"

If you want to put a literal $ in the output, you escape it from make by writing $$. Then, since this is in a double-quoted value you have to escape the literal $ from the shell as well, which uses \ and so you'd use:

@echo "DUPW $$$(VAR1).FILE*"

It might be simpler to understand if you switch to single quotes instead in your shell command, so the shell won't expand. Then you can forgo the backslash:

@echo 'DUPW $$$(VAR1).FILE*'

I have no idea what implementation of make is being used, but the behavior seen by User A is wrong / is not conforming to the POSIX standard for make.