英文:
How is ARM PPI is triggered and handled by an SMP ARM system?
问题
根据ARM GICv2规范，每个ARM核心有16个PPI。因此，我的理解是PPI对于每个ARM核心都是本地的，应该由核心进行信号传递和处理。
根据ARM GICv2规范，每个核心的PPI应具有相同的irq_num。
我无法弄清楚每个核心如何处理PPI。
以本地定时器（localtimer）为例，每个核心都有一个本地定时器，可以中断连接的核心。在这种情况下，如何安装/注册用于处理该定时器中断的软件中断处理程序？或者是否有全局中断处理程序用于每个核心的中断目标？
英文:
I am working on an ARMv7 project, which has 2 cores.
According to ARM GICv2 spec. there are 16 PPIs for each core.
So my understanding is the PPI is local to each ARM core, and it should be signaled to and handled by the core.
According to ARM GICv2 spec, the PPI should have the same irq_num for all cores.
I could NOT figure out how is a PPI handled by each core.
Let me use localtimer as an example, each core has an local timer which can interrupt the connected core, in this case, how to install/register the software interrupt handler for that timer interrupt? Or there is a global interrupt handler for the interrupt targets to each core?
答案1
得分: 1
我找到了答案。
根据GICv2规范，每个PPI都是每个核心私有的，不受ITARGETSRn寄存器的影响。一些GIC寄存器是分组的，因此每个核心都有自己的寄存器进行访问。
至于本地定时器示例，每个核心都应配置相同的GIC寄存器来设置定时器中断，当PPI触发时，定时器中断处理程序可以在每个核心上运行。
这是本地定时器中断，可用作调度时钟。
英文:
I found the answer to it.
As GICv2 spec. says, each PPI is private to each Core, and it is not impacted by ITARGETSRn register. Some GIC registers are banked, so each core has its own register to access.
As for the local timer example, each core should configure the same GIC registers to setup the timer interrupt, and the timer interrupt handler can be ran on each core when the PPI is triggered.
This is the local timer interrupt, which can be used as scheduling tick.
通过集体智慧和协作来改善编程学习和解决问题的方式。致力于成为全球开发者共同参与的知识库，让每个人都能够通过互相帮助和分享经验来进步。
评论